i2c: Replace the i2c API.
The new API is in use in depthcharge and is based around the "i2c_transfer" function instead of i2c_read and i2c_write. The new function takes an array of i2c_seg structures which represent each portion of the transfer after a start bit and before the stop bit. If there's more than one segment, they're seperated by repeated starts. Some wrapper functions have also been added which make certain common operations easy. These include reading or writing a byte from a register or reading or writing a blob of raw data. The i2c device drivers generally use these wrappers but can call the i2c_transfer function directly if the need something different. The tegra i2c driver was very similar to the one in depthcharge and was simple to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and replace the ones in coreboot. The Exynos 5420 driver was ported from the high speed portion of the one in coreboot and was straightforward to port back. The low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot and were replaced with the depthcharge implementation. BUG=None TEST=Built and booted on nyan with and without EFS. Built and booted on, pit and daisy. BRANCH=None Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193561 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe) This cherry-pick required additional changes to the following: src/cpu/allwinner/a10/twi.c src/drivers/xpowers/axp209/axp209.c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7 Reviewed-on: http://review.coreboot.org/7751 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Gabe Black
Marc Jones
parent
be6f8cb0f0
commit
cdb61a6f5d
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@ -109,8 +109,8 @@ static void i2c_send_stop(struct a1x_twi *twi)
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write32(reg32, &twi->ctl);
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}
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int i2c_read(unsigned bus, unsigned chip, unsigned addr,
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unsigned alen, uint8_t *buf, unsigned len)
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static int i2c_read(unsigned bus, unsigned chip, unsigned addr,
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uint8_t *buf, unsigned len)
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{
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unsigned count = len;
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enum twi_status expected_status;
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@ -169,8 +169,8 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr,
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return len;
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}
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int i2c_write(unsigned bus, unsigned chip, unsigned addr,
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unsigned alen, const uint8_t *buf, unsigned len)
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static int i2c_write(unsigned bus, unsigned chip, unsigned addr,
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const uint8_t *buf, unsigned len)
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{
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unsigned count = len;
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struct a1x_twi *twi = (void *)TWI_BASE(bus);
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@ -204,3 +204,35 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr,
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return len;
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}
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/*
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* This transfer function is not complete or correct, but it provides
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* the basic support that the above read and write functions previously
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* provided directly. It is extremely limited and not useful for
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* advanced drivers like TPM.
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*
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* TODO: Rewite the i2c_transfer and supporting functions
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*
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*/
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int i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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{
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struct i2c_seg *seg = segments;
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if (seg->read) {
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/* Read has one buf for the addr and one for the data */
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if (count != 2)
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return -1;
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if(i2c_read(bus, seg->chip, *seg->buf, seg[1].buf, seg[1].len) < 0)
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return -1;
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} else {
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/* Write buf has adder and data. */
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if (count != 1)
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return -1;
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if(i2c_write(bus, seg->chip, *seg->buf, seg->buf+1, seg->len-1) < 0)
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return -1;
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}
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return 0;
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}
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@ -79,10 +79,7 @@ int tis_init(void)
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* Probe TPM twice; the first probing might fail because TPM is asleep,
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* and the probing can wake up TPM.
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*/
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uint8_t tmp = 0;
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if (i2c_write(bus, chip, 0, 1, &tmp, sizeof(tmp)) &&
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i2c_write(bus, chip, 0, 1, &tmp, sizeof(tmp)))
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if (i2c_writeb(bus, chip, 0, 0) && i2c_writeb(bus, chip, 0, 0))
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return -1;
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return 0;
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@ -120,8 +120,7 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len)
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if ((tpm_dev.chip_type == SLB9635) || (tpm_dev.chip_type == UNKNOWN)) {
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/* slb9635 protocol should work in both cases */
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for (count = 0; count < MAX_COUNT; count++) {
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rc = i2c_write(tpm_dev.bus, tpm_dev.addr,
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0, 0, &addr, 1);
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rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr, &addr, 1);
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if (rc == 0)
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break; /* success, break to skip sleep */
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@ -137,8 +136,8 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len)
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*/
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for (count = 0; count < MAX_COUNT; count++) {
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udelay(SLEEP_DURATION);
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rc = i2c_read(tpm_dev.bus, tpm_dev.addr,
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0, 0, buffer, len);
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rc = i2c_read_raw(tpm_dev.bus, tpm_dev.addr,
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buffer, len);
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if (rc == 0)
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break; /* success, break to skip sleep */
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@ -150,9 +149,13 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len)
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* retries should usually not be needed, but are kept just to
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* be safe on the safe side.
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*/
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struct i2c_seg aseg = { .read = 0, .chip = tpm_dev.addr,
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.buf = &addr, .len = 1 };
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struct i2c_seg dseg = { .read = 1, .chip = tpm_dev.addr,
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.buf = buffer, .len = len };
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for (count = 0; count < MAX_COUNT; count++) {
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rc = i2c_read(tpm_dev.bus, tpm_dev.addr,
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addr, 1, buffer, len);
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rc = i2c_transfer(tpm_dev.bus, &aseg, 1) ||
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i2c_transfer(tpm_dev.bus, &dseg, 1);
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if (rc == 0)
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break; /* break here to skip sleep */
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udelay(SLEEP_DURATION);
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@ -186,7 +189,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len,
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if (!tpm_dev.bus)
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return -1;
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for (count = 0; count < max_count; count++) {
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rc = i2c_write(tpm_dev.bus, tpm_dev.addr, 0, 0,
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rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr,
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tpm_dev.buf, len + 1);
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if (rc == 0)
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break; /* success, break to skip sleep */
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@ -93,7 +93,7 @@ struct max77686_para max77686_param[] = {/*{vol_addr, vol_bitpos,
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static inline int max77686_i2c_write(unsigned int bus, unsigned char chip_addr,
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unsigned int reg, unsigned char val)
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{
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return i2c_write(bus, chip_addr, reg, 1, &val, 1);
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return i2c_writeb(bus, chip_addr, reg, val);
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}
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/*
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@ -107,7 +107,7 @@ static inline int max77686_i2c_write(unsigned int bus, unsigned char chip_addr,
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static inline int max77686_i2c_read(unsigned int bus, unsigned char chip_addr,
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unsigned int reg, unsigned char *val)
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{
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return i2c_read(bus, chip_addr, reg, 1, val, 1);
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return i2c_readb(bus, chip_addr, reg, (uint8_t *)val);
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}
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/*
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@ -31,7 +31,6 @@ void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base,
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for (i = 0; i < parade_write_count; i++) {
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const struct parade_write *w = ¶de_writes[i];
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i2c_write(bus, chip_base + w->offset, w->reg, sizeof(w->reg),
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&w->val, sizeof(w->val));
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i2c_writeb(bus, chip_base + w->offset, w->reg, w->val);
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}
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}
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@ -64,7 +64,7 @@ static int tps65090_i2c_write(unsigned int bus,
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{
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int ret;
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ret = i2c_write(bus, TPS65090_I2C_ADDR, reg_addr, 1, &value, 1);
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ret = i2c_writeb(bus, TPS65090_I2C_ADDR, reg_addr, value);
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printk(BIOS_DEBUG, "%s: reg=%#x, value=%#x, ret=%d\n",
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__func__, reg_addr, value, ret);
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return ret;
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@ -76,7 +76,7 @@ static int tps65090_i2c_read(unsigned int bus,
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int ret;
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printk(BIOS_DEBUG, "%s: reg=%#x, ", __func__, reg_addr);
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ret = i2c_read(bus, TPS65090_I2C_ADDR, reg_addr, 1, value, 1);
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ret = i2c_readb(bus, TPS65090_I2C_ADDR, reg_addr, value);
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if (ret)
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printk(BIOS_DEBUG, "fail, ret=%d\n", ret);
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else
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@ -47,12 +47,12 @@ enum registers {
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*/
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static int axp209_read(u8 bus, u8 reg, u8 *val)
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{
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return i2c_read(bus, AXP209_I2C_ADDR, reg, 1, val, 1);
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return i2c_readb(bus, AXP209_I2C_ADDR, reg, val);
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}
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static int axp209_write(u8 bus, u8 reg, u8 val)
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{
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return i2c_write(bus, AXP209_I2C_ADDR, reg, 1, &val, 1);
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return i2c_writeb(bus, AXP209_I2C_ADDR, reg, val);
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}
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/**
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@ -116,13 +116,13 @@ int google_chromeec_command(struct chromeec_command *cec_command)
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/* Start I2C communication */
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i2c_dump(bus, chip, (const uint8_t *)&cmd, size_i2c_cmd);
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if (i2c_write(bus, chip, 0, 0, (uint8_t *)&cmd, size_i2c_cmd) != 0) {
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if (i2c_write_raw(bus, chip, (uint8_t *)&cmd, size_i2c_cmd) != 0) {
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printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n",
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__func__, bus, chip);
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cec_command->cmd_code = EC_RES_ERROR;
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return 1;
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}
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if (i2c_read(bus, chip, 0, 0, (uint8_t *)&resp, size_i2c_resp) != 0) {
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if (i2c_read_raw(bus, chip, (uint8_t *)&resp, size_i2c_resp) != 0) {
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printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n",
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__func__, bus, chip);
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cec_command->cmd_code = EC_RES_ERROR;
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,11 +21,83 @@
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#define _DEVICE_I2C_H_
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#include <stdint.h>
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#include <stdlib.h>
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/* note: chip is the 7-bit I2C address */
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int i2c_read(unsigned bus, unsigned chip, unsigned addr,
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unsigned alen, uint8_t *buf, unsigned len);
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int i2c_write(unsigned bus, unsigned chip, unsigned addr,
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unsigned alen, const uint8_t *buf, unsigned len);
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struct i2c_seg
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{
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int read;
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uint8_t chip;
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uint8_t *buf;
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int len;
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};
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int i2c_transfer(unsigned bus, struct i2c_seg *segments, int count);
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/*
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* Read a raw chunk of data in one segment and one frame.
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*
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* [start][slave addr][r][data][stop]
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*/
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static inline int i2c_read_raw(unsigned bus, uint8_t chip, uint8_t *data,
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int len)
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{
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struct i2c_seg seg =
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{ .read = 1, .chip = chip, .buf = data, .len = len };
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return i2c_transfer(bus, &seg, 1);
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}
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/*
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* Write a raw chunk of data in one segment and one frame.
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*
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* [start][slave addr][w][data][stop]
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*/
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static inline int i2c_write_raw(unsigned bus, uint8_t chip, uint8_t *data,
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int len)
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{
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struct i2c_seg seg =
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{ .read = 0, .chip = chip, .buf = data, .len = len };
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return i2c_transfer(bus, &seg, 1);
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}
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/**
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* Read a byte with two segments in one frame
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*
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* [start][slave addr][w][register addr][start][slave addr][r][data][stop]
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*/
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static inline int i2c_readb(unsigned bus, uint8_t chip, uint8_t reg,
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uint8_t *data)
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{
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struct i2c_seg seg[2];
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seg[0].read = 0;
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seg[0].chip = chip;
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seg[0].buf = ®
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seg[0].len = 1;
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seg[1].read = 1;
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seg[1].chip = chip;
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seg[1].buf = data;
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seg[1].len = 1;
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return i2c_transfer(bus, seg, ARRAY_SIZE(seg));
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}
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/**
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* Write a byte with one segment in one frame.
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*
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* [start][slave addr][w][register addr][data][stop]
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*/
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static inline int i2c_writeb(unsigned bus, uint8_t chip, uint8_t reg,
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uint8_t data)
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{
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struct i2c_seg seg;
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uint8_t buf[] = {reg, data};
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seg.read = 0;
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seg.chip = chip;
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seg.buf = buf;
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seg.len = ARRAY_SIZE(buf);
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return i2c_transfer(bus, &seg, 1);
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}
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#endif /* _DEVICE_I2C_H_ */
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@ -34,6 +34,7 @@
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#include <soc/samsung/exynos5250/i2c.h>
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#include <soc/samsung/exynos5250/dp-core.h>
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#include <soc/samsung/exynos5250/dp.h>
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#include <soc/samsung/exynos5250/periph.h>
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#include <soc/samsung/exynos5250/usb.h>
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#include "exynos5250.h"
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@ -59,7 +59,7 @@ static struct as3722_init_reg init_list[] = {
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
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{
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i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
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i2c_writeb(bus, AS3722_I2C_ADDR, reg, val);
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if (do_delay)
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udelay(500);
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}
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@ -59,7 +59,7 @@ static struct as3722_init_reg init_list[] = {
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
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{
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i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
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i2c_writeb(bus, AS3722_I2C_ADDR, reg, val);
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if (do_delay)
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udelay(500);
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}
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@ -59,7 +59,7 @@ static struct as3722_init_reg init_list[] = {
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
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{
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i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
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i2c_writeb(bus, AS3722_I2C_ADDR, reg, val);
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if (do_delay)
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udelay(500);
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}
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@ -32,6 +32,7 @@
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#include <soc/samsung/exynos5420/cpu.h>
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#include <soc/samsung/exynos5420/gpio.h>
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#include <soc/samsung/exynos5420/power.h>
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#include <soc/samsung/exynos5420/periph.h>
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#include <soc/samsung/exynos5420/i2c.h>
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#include <soc/samsung/exynos5420/dp.h>
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#include <soc/samsung/exynos5420/fimd.h>
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@ -97,13 +97,10 @@ static int setup_power(int is_resume)
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uint8_t reg = pmic_writes[i].reg;
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if (pmic_writes[i].or_orig)
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error |= i2c_read(4, MAX77802_I2C_ADDR,
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reg, sizeof(reg),
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&data, sizeof(data));
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error |= i2c_readb(4, MAX77802_I2C_ADDR, reg, &data);
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data |= pmic_writes[i].val;
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error |= i2c_write(4, MAX77802_I2C_ADDR,
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reg, sizeof(reg),
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&data, sizeof(data));
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error |= i2c_writeb(4, MAX77802_I2C_ADDR, reg, data);
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}
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return error;
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@ -130,43 +130,35 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart,
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data, data_len);
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}
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|
||||
static int i2c_readwrite(unsigned bus, unsigned chip, unsigned addr,
|
||||
unsigned alen, uint8_t *buf, unsigned len, int read)
|
||||
static int i2c_transfer_segment(unsigned bus, unsigned chip, int restart,
|
||||
int read, void *buf, int len)
|
||||
{
|
||||
const uint32_t max_payload =
|
||||
(IOHEADER_PAYLOADSIZE_MASK + 1) >> IOHEADER_PAYLOADSIZE_SHIFT;
|
||||
uint8_t abuf[sizeof(addr)];
|
||||
|
||||
int i;
|
||||
for (i = 0; i < alen; i++)
|
||||
abuf[i] = addr >> ((alen - i - 1) * 8);
|
||||
|
||||
if (tegra_i2c_request(bus, chip, !read, 0, 0, abuf, alen))
|
||||
return -1;
|
||||
|
||||
while (len) {
|
||||
int todo = MIN(len, max_payload);
|
||||
int cont = (todo < len);
|
||||
if (tegra_i2c_request(bus, chip, cont, 0, read, buf, todo)) {
|
||||
// We should reset the controller here.
|
||||
if (tegra_i2c_request(bus, chip, cont, restart,
|
||||
read, buf, todo))
|
||||
return -1;
|
||||
}
|
||||
len -= todo;
|
||||
buf += todo;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_read(unsigned bus, unsigned chip, unsigned addr,
|
||||
unsigned alen, uint8_t *buf, unsigned len)
|
||||
int i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
|
||||
{
|
||||
return i2c_readwrite(bus, chip, addr, alen, buf, len, 1);
|
||||
}
|
||||
struct i2c_seg *seg = segments;
|
||||
|
||||
int i2c_write(unsigned bus, unsigned chip, unsigned addr,
|
||||
unsigned alen, const uint8_t *buf, unsigned len)
|
||||
{
|
||||
return i2c_readwrite(bus, chip, addr, alen, (void *)buf, len, 0);
|
||||
int i;
|
||||
for (i = 0; i < count; seg++, i++) {
|
||||
if (i2c_transfer_segment(bus, seg->chip, i < count - 1,
|
||||
seg->read, seg->buf, seg->len))
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i2c_init(unsigned bus)
|
||||
|
|
|
|||
|
|
@ -18,119 +18,263 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/i2c.h>
|
||||
#include "clk.h"
|
||||
#include "i2c.h"
|
||||
#include "periph.h"
|
||||
|
||||
#define I2C_WRITE 0
|
||||
#define I2C_READ 1
|
||||
|
||||
#define I2C_OK 0
|
||||
#define I2C_NOK 1
|
||||
#define I2C_NACK 2
|
||||
#define I2C_NOK_LA 3 /* Lost arbitration */
|
||||
#define I2C_NOK_TOUT 4 /* time out */
|
||||
|
||||
#define I2CSTAT_BSY 0x20 /* Busy bit */
|
||||
#define I2CSTAT_NACK 0x01 /* Nack bit */
|
||||
#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
|
||||
#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
|
||||
#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
|
||||
#define I2C_MODE_MR 0x80 /* Master Receive Mode */
|
||||
#define I2C_START_STOP 0x20 /* START / STOP */
|
||||
#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
|
||||
|
||||
/* The timeouts we live by */
|
||||
enum {
|
||||
I2C_XFER_TIMEOUT_MS = 35, /* xfer to complete */
|
||||
I2C_INIT_TIMEOUT_MS = 1000, /* bus free on init */
|
||||
I2C_IDLE_TIMEOUT_MS = 100, /* waiting for bus idle */
|
||||
I2C_STOP_TIMEOUT_US = 200, /* waiting for stop events */
|
||||
struct __attribute__ ((packed)) i2c_regs
|
||||
{
|
||||
uint8_t con;
|
||||
uint8_t _1[3];
|
||||
uint8_t stat;
|
||||
uint8_t _2[3];
|
||||
uint8_t add;
|
||||
uint8_t _3[3];
|
||||
uint8_t ds;
|
||||
uint8_t _4[3];
|
||||
uint8_t lc;
|
||||
uint8_t _5[3];
|
||||
};
|
||||
|
||||
static struct s3c24x0_i2c_bus i2c_buses[] = {
|
||||
struct s3c24x0_i2c_bus {
|
||||
int bus_num;
|
||||
struct i2c_regs *regs;
|
||||
enum periph_id periph_id;
|
||||
};
|
||||
|
||||
enum {
|
||||
I2cConIntPending = 0x1 << 4,
|
||||
I2cConIntEn = 0x1 << 5,
|
||||
I2cConAckGen = 0x1 << 7
|
||||
};
|
||||
|
||||
enum {
|
||||
I2cStatAck = 0x1 << 0,
|
||||
I2cStatAddrZero = 0x1 << 1,
|
||||
I2cStatAddrSlave = 0x1 << 2,
|
||||
I2cStatArb = 0x1 << 3,
|
||||
I2cStatEnable = 0x1 << 4,
|
||||
I2cStatStartStop = 0x1 << 5,
|
||||
I2cStatBusy = 0x1 << 5,
|
||||
|
||||
I2cStatModeMask = 0x3 << 6,
|
||||
I2cStatSlaveRecv = 0x0 << 6,
|
||||
I2cStatSlaveXmit = 0x1 << 6,
|
||||
I2cStatMasterRecv = 0x2 << 6,
|
||||
I2cStatMasterXmit = 0x3 << 6
|
||||
};
|
||||
|
||||
static struct s3c24x0_i2c_bus i2c_busses[] = {
|
||||
{
|
||||
.bus_num = 0,
|
||||
.regs = (struct s3c24x0_i2c *)0x12c60000,
|
||||
.regs = (void *)0x12c60000,
|
||||
.periph_id = PERIPH_ID_I2C0,
|
||||
},
|
||||
{
|
||||
.bus_num = 1,
|
||||
.regs = (struct s3c24x0_i2c *)0x12c70000,
|
||||
.regs = (void *)0x12c70000,
|
||||
.periph_id = PERIPH_ID_I2C1,
|
||||
},
|
||||
{
|
||||
.bus_num = 2,
|
||||
.regs = (struct s3c24x0_i2c *)0x12c80000,
|
||||
.regs = (void *)0x12c80000,
|
||||
.periph_id = PERIPH_ID_I2C2,
|
||||
},
|
||||
{
|
||||
.bus_num = 3,
|
||||
.regs = (struct s3c24x0_i2c *)0x12c90000,
|
||||
.regs = (void *)0x12c90000,
|
||||
.periph_id = PERIPH_ID_I2C3,
|
||||
},
|
||||
{
|
||||
.bus_num = 4,
|
||||
.regs = (struct s3c24x0_i2c *)0x12ca0000,
|
||||
.regs = (void *)0x12ca0000,
|
||||
.periph_id = PERIPH_ID_I2C4,
|
||||
},
|
||||
{
|
||||
.bus_num = 5,
|
||||
.regs = (struct s3c24x0_i2c *)0x12cb0000,
|
||||
.regs = (void *)0x12cb0000,
|
||||
.periph_id = PERIPH_ID_I2C5,
|
||||
},
|
||||
{
|
||||
.bus_num = 6,
|
||||
.regs = (struct s3c24x0_i2c *)0x12cc0000,
|
||||
.regs = (void *)0x12cc0000,
|
||||
.periph_id = PERIPH_ID_I2C6,
|
||||
},
|
||||
{
|
||||
.bus_num = 7,
|
||||
.regs = (struct s3c24x0_i2c *)0x12cd0000,
|
||||
.regs = (void *)0x12cd0000,
|
||||
.periph_id = PERIPH_ID_I2C7,
|
||||
},
|
||||
};
|
||||
|
||||
static int WaitForXfer(struct s3c24x0_i2c *i2c)
|
||||
|
||||
|
||||
|
||||
static int i2c_int_pending(struct i2c_regs *regs)
|
||||
{
|
||||
return readb(®s->con) & I2cConIntPending;
|
||||
}
|
||||
|
||||
static void i2c_clear_int(struct i2c_regs *regs)
|
||||
{
|
||||
writeb(readb(®s->con) & ~I2cConIntPending, ®s->con);
|
||||
}
|
||||
|
||||
static void i2c_ack_enable(struct i2c_regs *regs)
|
||||
{
|
||||
writeb(readb(®s->con) | I2cConAckGen, ®s->con);
|
||||
}
|
||||
|
||||
static void i2c_ack_disable(struct i2c_regs *regs)
|
||||
{
|
||||
writeb(readb(®s->con) & ~I2cConAckGen, ®s->con);
|
||||
}
|
||||
|
||||
static int i2c_got_ack(struct i2c_regs *regs)
|
||||
{
|
||||
return !(readb(®s->stat) & I2cStatAck);
|
||||
}
|
||||
|
||||
static int i2c_wait_for_idle(struct i2c_regs *regs)
|
||||
{
|
||||
int timeout = 1000 * 100; // 1s.
|
||||
while (timeout--) {
|
||||
if (!(readb(®s->stat) & I2cStatBusy))
|
||||
return 0;
|
||||
udelay(10);
|
||||
}
|
||||
printk(BIOS_ERR, "I2C timeout waiting for idle.\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int i2c_wait_for_int(struct i2c_regs *regs)
|
||||
{
|
||||
int timeout = 1000 * 100; // 1s.
|
||||
while (timeout--) {
|
||||
if (i2c_int_pending(regs))
|
||||
return 0;
|
||||
udelay(10);
|
||||
}
|
||||
printk(BIOS_ERR, "I2C timeout waiting for I2C interrupt.\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static int i2c_send_stop(struct i2c_regs *regs)
|
||||
{
|
||||
uint8_t mode = readb(®s->stat) & (I2cStatModeMask);
|
||||
writeb(mode | I2cStatEnable, ®s->stat);
|
||||
i2c_clear_int(regs);
|
||||
return i2c_wait_for_idle(regs);
|
||||
}
|
||||
|
||||
static int i2c_send_start(struct i2c_regs *regs, int read, int chip)
|
||||
{
|
||||
writeb(chip << 1, ®s->ds);
|
||||
uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit;
|
||||
writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat);
|
||||
i2c_clear_int(regs);
|
||||
|
||||
if (i2c_wait_for_int(regs))
|
||||
return 1;
|
||||
|
||||
if (!i2c_got_ack(regs)) {
|
||||
// Nobody home, but they may just be asleep.
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len)
|
||||
{
|
||||
ASSERT(len);
|
||||
|
||||
i2c_ack_enable(regs);
|
||||
|
||||
int i;
|
||||
for (i = 0; i < len; i++) {
|
||||
writeb(data[i], ®s->ds);
|
||||
|
||||
i = I2C_XFER_TIMEOUT_MS * 20;
|
||||
while (!(readl(&i2c->iiccon) & I2CCON_IRPND)) {
|
||||
if (i == 0) {
|
||||
printk(BIOS_ERR, "%s: i2c xfer timeout\n", __func__);
|
||||
return I2C_NOK_TOUT;
|
||||
i2c_clear_int(regs);
|
||||
if (i2c_wait_for_int(regs))
|
||||
return 1;
|
||||
|
||||
if (!i2c_got_ack(regs)) {
|
||||
printk(BIOS_INFO, "I2c nacked.\n");
|
||||
return 1;
|
||||
}
|
||||
udelay(50);
|
||||
i--;
|
||||
}
|
||||
|
||||
return I2C_OK;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int IsACK(struct s3c24x0_i2c *i2c)
|
||||
static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len)
|
||||
{
|
||||
return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
|
||||
ASSERT(len);
|
||||
|
||||
i2c_ack_enable(regs);
|
||||
|
||||
int i;
|
||||
for (i = 0; i < len; i++) {
|
||||
if (i == len - 1)
|
||||
i2c_ack_disable(regs);
|
||||
|
||||
i2c_clear_int(regs);
|
||||
if (i2c_wait_for_int(regs))
|
||||
return 1;
|
||||
|
||||
data[i] = readb(®s->ds);
|
||||
}
|
||||
|
||||
static void ReadWriteByte(struct s3c24x0_i2c *i2c)
|
||||
{
|
||||
uint32_t x;
|
||||
|
||||
x = readl(&i2c->iiccon);
|
||||
writel(x & ~I2CCON_IRPND, &i2c->iiccon);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd)
|
||||
int i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c = &i2c_busses[bus];
|
||||
struct i2c_regs *regs = i2c->regs;
|
||||
int res = 0;
|
||||
|
||||
if (!regs || i2c_wait_for_idle(regs))
|
||||
return 1;
|
||||
|
||||
writeb(I2cStatMasterXmit | I2cStatEnable, ®s->stat);
|
||||
|
||||
int i;
|
||||
for (i = 0; i < seg_count; i++) {
|
||||
struct i2c_seg *seg = &segments[i];
|
||||
|
||||
res = i2c_send_start(regs, seg->read, seg->chip);
|
||||
if (res)
|
||||
break;
|
||||
if (seg->read)
|
||||
res = i2c_recv_buf(regs, seg->buf, seg->len);
|
||||
else
|
||||
res = i2c_xmit_buf(regs, seg->buf, seg->len);
|
||||
if (res)
|
||||
break;
|
||||
}
|
||||
|
||||
return i2c_send_stop(regs) || res;
|
||||
}
|
||||
|
||||
void i2c_init(unsigned bus, int speed, int slaveadd)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c = &i2c_busses[bus];
|
||||
|
||||
unsigned long freq, pres = 16, div;
|
||||
unsigned long val;
|
||||
|
||||
freq = clock_get_periph_rate(bus->periph_id);
|
||||
/* calculate prescaler and divisor values */
|
||||
freq = clock_get_periph_rate(i2c->periph_id);
|
||||
// Calculate prescaler and divisor values.
|
||||
if ((freq / pres / (16 + 1)) > speed)
|
||||
/* set prescaler to 512 */
|
||||
pres = 512;
|
||||
|
|
@ -140,264 +284,13 @@ static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd)
|
|||
while ((freq / pres / (div + 1)) > speed)
|
||||
div++;
|
||||
|
||||
/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
|
||||
val = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
|
||||
writel(val, &bus->regs->iiccon);
|
||||
// Set prescaler, divisor according to freq, also set ACKGEN, IRQ.
|
||||
val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0);
|
||||
writel(val, &i2c->regs->con);
|
||||
|
||||
/* init to SLAVE RECEIVE mode and clear I2CADDn */
|
||||
writel(0, &bus->regs->iicstat);
|
||||
writel(slaveadd, &bus->regs->iicadd);
|
||||
/* program Master Transmit (and implicit STOP) */
|
||||
writel(I2C_MODE_MT | I2C_TXRX_ENA, &bus->regs->iicstat);
|
||||
}
|
||||
|
||||
/*
|
||||
* MULTI BUS I2C support
|
||||
*/
|
||||
static void i2c_bus_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd)
|
||||
{
|
||||
i2c_ch_init(bus, speed, slaveadd);
|
||||
}
|
||||
|
||||
/*
|
||||
* Verify the whether I2C ACK was received or not
|
||||
*
|
||||
* @param i2c pointer to I2C register base
|
||||
* @param buf array of data
|
||||
* @param len length of data
|
||||
* return I2C_OK when transmission done
|
||||
* I2C_NACK otherwise
|
||||
*/
|
||||
static int i2c_send_verify(struct s3c24x0_i2c *i2c, unsigned char buf[],
|
||||
unsigned char len)
|
||||
{
|
||||
int i, result = I2C_OK;
|
||||
|
||||
if (IsACK(i2c)) {
|
||||
for (i = 0; (i < len) && (result == I2C_OK); i++) {
|
||||
writel(buf[i], &i2c->iicds);
|
||||
ReadWriteByte(i2c);
|
||||
result = WaitForXfer(i2c);
|
||||
if (result == I2C_OK && !IsACK(i2c))
|
||||
result = I2C_NACK;
|
||||
}
|
||||
} else {
|
||||
result = I2C_NACK;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
void i2c_init(unsigned bus_num, int speed, int slaveadd)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c;
|
||||
int i;
|
||||
|
||||
i2c = &i2c_buses[bus_num];
|
||||
i2c_bus_init(i2c, speed, slaveadd);
|
||||
|
||||
/* wait for some time to give previous transfer a chance to finish */
|
||||
i = I2C_INIT_TIMEOUT_MS * 20;
|
||||
while ((readl(&i2c->regs->iicstat) & I2CSTAT_BSY) && (i > 0)) {
|
||||
udelay(50);
|
||||
i--;
|
||||
}
|
||||
|
||||
i2c_ch_init(i2c, speed, slaveadd);
|
||||
}
|
||||
|
||||
/*
|
||||
* Send a STOP event and wait for it to have completed
|
||||
*
|
||||
* @param mode If it is a master transmitter or receiver
|
||||
* @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise
|
||||
*/
|
||||
static int i2c_send_stop(struct s3c24x0_i2c *i2c, int mode)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
/* Setting the STOP event to fire */
|
||||
writel(mode | I2C_TXRX_ENA, &i2c->iicstat);
|
||||
ReadWriteByte(i2c);
|
||||
|
||||
/* Wait for the STOP to send and the bus to go idle */
|
||||
for (timeout = I2C_STOP_TIMEOUT_US; timeout > 0; timeout -= 5) {
|
||||
if (!(readl(&i2c->iicstat) & I2CSTAT_BSY))
|
||||
return I2C_OK;
|
||||
udelay(5);
|
||||
}
|
||||
|
||||
return I2C_NOK_TOUT;
|
||||
}
|
||||
|
||||
/*
|
||||
* cmd_type is 0 for write, 1 for read.
|
||||
*
|
||||
* addr_len can take any value from 0-255, it is only limited
|
||||
* by the char, we could make it larger if needed. If it is
|
||||
* 0 we skip the address write cycle.
|
||||
*/
|
||||
static int i2c_transfer(struct s3c24x0_i2c *i2c,
|
||||
unsigned char cmd_type,
|
||||
unsigned char chip,
|
||||
unsigned char addr[],
|
||||
unsigned char addr_len,
|
||||
unsigned char data[],
|
||||
unsigned short data_len)
|
||||
{
|
||||
int i, result, stop_bit_result;
|
||||
uint32_t x;
|
||||
|
||||
if (data == 0 || data_len == 0) {
|
||||
/* Don't support data transfer of no length or to address 0 */
|
||||
printk(BIOS_ERR, "i2c_transfer: bad call\n");
|
||||
return I2C_NOK;
|
||||
}
|
||||
|
||||
/* Check I2C bus idle */
|
||||
i = I2C_IDLE_TIMEOUT_MS * 20;
|
||||
while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
|
||||
udelay(50);
|
||||
i--;
|
||||
}
|
||||
|
||||
if (readl(&i2c->iicstat) & I2CSTAT_BSY) {
|
||||
printk(BIOS_ERR, "%s: bus busy\n", __func__);
|
||||
return I2C_NOK_TOUT;
|
||||
}
|
||||
|
||||
x = readl(&i2c->iiccon);
|
||||
writel(x | I2CCON_ACKGEN, &i2c->iiccon);
|
||||
|
||||
if (addr && addr_len) {
|
||||
writel(chip, &i2c->iicds);
|
||||
/* send START */
|
||||
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
|
||||
&i2c->iicstat);
|
||||
if (WaitForXfer(i2c) == I2C_OK)
|
||||
result = i2c_send_verify(i2c, addr, addr_len);
|
||||
else
|
||||
result = I2C_NACK;
|
||||
} else
|
||||
result = I2C_NACK;
|
||||
|
||||
switch (cmd_type) {
|
||||
case I2C_WRITE:
|
||||
if (result == I2C_OK)
|
||||
result = i2c_send_verify(i2c, data, data_len);
|
||||
else {
|
||||
writel(chip, &i2c->iicds);
|
||||
/* send START */
|
||||
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
|
||||
&i2c->iicstat);
|
||||
if (WaitForXfer(i2c) == I2C_OK)
|
||||
result = i2c_send_verify(i2c, data, data_len);
|
||||
}
|
||||
|
||||
if (result == I2C_OK)
|
||||
result = WaitForXfer(i2c);
|
||||
|
||||
stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MT);
|
||||
break;
|
||||
|
||||
case I2C_READ:
|
||||
{
|
||||
int was_ok = (result == I2C_OK);
|
||||
|
||||
writel(chip, &i2c->iicds);
|
||||
/* resend START */
|
||||
writel(I2C_MODE_MR | I2C_TXRX_ENA |
|
||||
I2C_START_STOP, &i2c->iicstat);
|
||||
ReadWriteByte(i2c);
|
||||
result = WaitForXfer(i2c);
|
||||
|
||||
if (was_ok || IsACK(i2c)) {
|
||||
i = 0;
|
||||
while ((i < data_len) && (result == I2C_OK)) {
|
||||
/* disable ACK for final READ */
|
||||
if (i == data_len - 1) {
|
||||
x = readl(&i2c->iiccon) & ~I2CCON_ACKGEN;
|
||||
writel(x, &i2c->iiccon);
|
||||
}
|
||||
ReadWriteByte(i2c);
|
||||
result = WaitForXfer(i2c);
|
||||
data[i] = readl(&i2c->iicds);
|
||||
i++;
|
||||
}
|
||||
} else {
|
||||
result = I2C_NACK;
|
||||
}
|
||||
|
||||
stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MR);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
printk(BIOS_ERR, "i2c_transfer: bad call\n");
|
||||
result = stop_bit_result = I2C_NOK;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the transmission went fine, then only the stop bit was left to
|
||||
* fail. Otherwise, the real failure we're interested in came before
|
||||
* that, during the actual transmission.
|
||||
*/
|
||||
return (result == I2C_OK) ? stop_bit_result : result;
|
||||
}
|
||||
|
||||
int i2c_read(unsigned bus, unsigned chip, unsigned addr,
|
||||
unsigned alen, uint8_t *buf, unsigned len)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c;
|
||||
unsigned char xaddr[4];
|
||||
int ret;
|
||||
|
||||
if (alen > 4) {
|
||||
printk(BIOS_ERR, "I2C read: addr len %d not supported\n", alen);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (alen > 0) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
|
||||
i2c = &i2c_buses[bus];
|
||||
ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen],
|
||||
alen, buf, len);
|
||||
if (ret) {
|
||||
printk(BIOS_ERR, "I2c read: failed %d\n", ret);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write(unsigned bus, unsigned chip, unsigned addr,
|
||||
unsigned alen, const uint8_t *buf, unsigned len)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c;
|
||||
unsigned char xaddr[4];
|
||||
int ret;
|
||||
|
||||
if (alen > 4) {
|
||||
printk(BIOS_ERR, "I2C write: addr len %d not supported\n",
|
||||
alen);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (alen > 0) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
|
||||
i2c = &i2c_buses[bus];
|
||||
ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen],
|
||||
alen, (void *)buf, len);
|
||||
|
||||
return ret != 0;
|
||||
// Init to SLAVE RECEIVE mode and clear I2CADDn.
|
||||
writel(0, &i2c->regs->stat);
|
||||
writel(slaveadd, &i2c->regs->add);
|
||||
// program Master Transmit (and implicit STOP).
|
||||
writel(I2cStatMasterXmit | I2cStatEnable, &i2c->regs->stat);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,22 +20,6 @@
|
|||
#ifndef CPU_SAMSUNG_EXYNOS5250_I2C_H
|
||||
#define CPU_SAMSUNG_EXYNOS5250_I2C_H
|
||||
|
||||
#include "periph.h"
|
||||
|
||||
struct s3c24x0_i2c {
|
||||
u32 iiccon;
|
||||
u32 iicstat;
|
||||
u32 iicadd;
|
||||
u32 iicds;
|
||||
u32 iiclc;
|
||||
};
|
||||
|
||||
struct s3c24x0_i2c_bus {
|
||||
int bus_num;
|
||||
struct s3c24x0_i2c *regs;
|
||||
enum periph_id periph_id;
|
||||
};
|
||||
|
||||
void i2c_init(unsigned bus, int speed, int slaveadd);
|
||||
|
||||
#endif /* CPU_SAMSUNG_EXYNOS5250_I2C_H */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -20,60 +20,6 @@
|
|||
#ifndef CPU_SAMSUNG_EXYNOS5420_I2C_H
|
||||
#define CPU_SAMSUNG_EXYNOS5420_I2C_H
|
||||
|
||||
#include "periph.h"
|
||||
|
||||
struct s3c24x0_i2c {
|
||||
u32 iiccon;
|
||||
u32 iicstat;
|
||||
u32 iicadd;
|
||||
u32 iicds;
|
||||
u32 iiclc;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct exynos5_hsi2c {
|
||||
u32 usi_ctl;
|
||||
u32 usi_fifo_ctl;
|
||||
u32 usi_trailing_ctl;
|
||||
u32 usi_clk_ctl;
|
||||
u32 usi_clk_slot;
|
||||
u32 spi_ctl;
|
||||
u32 uart_ctl;
|
||||
u32 res1;
|
||||
u32 usi_int_en;
|
||||
u32 usi_int_stat;
|
||||
u32 usi_modem_stat;
|
||||
u32 usi_error_stat;
|
||||
u32 usi_fifo_stat;
|
||||
u32 usi_txdata;
|
||||
u32 usi_rxdata;
|
||||
u32 res2;
|
||||
u32 usi_conf;
|
||||
u32 usi_auto_conf;
|
||||
u32 usi_timeout;
|
||||
u32 usi_manual_cmd;
|
||||
u32 usi_trans_status;
|
||||
u32 usi_timing_hs1;
|
||||
u32 usi_timing_hs2;
|
||||
u32 usi_timing_hs3;
|
||||
u32 usi_timing_fs1;
|
||||
u32 usi_timing_fs2;
|
||||
u32 usi_timing_fs3;
|
||||
u32 usi_timing_sla;
|
||||
u32 i2c_addr;
|
||||
} __attribute__ ((packed));
|
||||
check_member(exynos5_hsi2c, i2c_addr, 0x70);
|
||||
|
||||
struct s3c24x0_i2c_bus {
|
||||
int bus_num;
|
||||
struct s3c24x0_i2c *regs;
|
||||
enum periph_id periph_id;
|
||||
struct exynos5_hsi2c *hsregs;
|
||||
int is_highspeed; /* High speed type, rather than I2C */
|
||||
int id;
|
||||
unsigned clk_cycle;
|
||||
unsigned clk_div;
|
||||
};
|
||||
|
||||
void i2c_init(unsigned bus, int speed, int slaveadd);
|
||||
|
||||
#endif /* CPU_SAMSUNG_EXYNOS5420_I2C_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue