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soc/rockchip/rk3288/clock.c: Remove trailing semicolon 

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0d03bd43b33570ee50f145ea6fd716c4072a11d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Elyes Haouas 2022-09-29 12:24:53 +02:00 committed by Felix Held
parent fb0a751c76
commit cdf99a9b3e
1 changed files with 1 additions and 1 deletions
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src/soc/rockchip/rk3288/clock.c
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@ -53,7 +53,7 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
(_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
"divisors on line " STRINGIFY(__LINE__)); "divisors on line " STRINGIFY(__LINE__))
/* Keep divisors as low as possible to reduce jitter and power usage. */ /* Keep divisors as low as possible to reduce jitter and power usage. */
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);