Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -3401,6 +3401,8 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
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// FIXME: skip for Ax
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// FIXME: skip for Ax
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dev = pDCTstat->dev_dct;
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/* Tri-state unused ODTs when motherboard termination is available */
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/* Tri-state unused ODTs when motherboard termination is available */
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max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
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max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
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odt = 0x0F; /* tristate all the pins then clear the used ones. */
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odt = 0x0F; /* tristate all the pins then clear the used ones. */
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@ -197,13 +197,16 @@ u16 mctGet_NVbits(u8 index)
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case NV_CS_SpareCTL:
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case NV_CS_SpareCTL:
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val = 0; /* Disabled */
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val = 0; /* Disabled */
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//val = 1; /* Enabled */
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//val = 1; /* Enabled */
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break;
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case NV_SyncOnUnEccEn:
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case NV_SyncOnUnEccEn:
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val = 0; /* Disabled */
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val = 0; /* Disabled */
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//val = 1; /* Enabled */
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//val = 1; /* Enabled */
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break;
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case NV_Unganged:
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case NV_Unganged:
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/* channel interleave is better performance than ganged mode at this time */
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/* channel interleave is better performance than ganged mode at this time */
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val = 1; /* Enabled */
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val = 1; /* Enabled */
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//val = 0; /* Disabled */
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//val = 0; /* Disabled */
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break;
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case NV_ChannelIntlv:
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case NV_ChannelIntlv:
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val = 5; /* Not currently checked in mctchi_d.c */
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val = 5; /* Not currently checked in mctchi_d.c */
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/* Bit 0 = 0 - Disable
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/* Bit 0 = 0 - Disable
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@ -213,7 +216,7 @@ u16 mctGet_NVbits(u8 index)
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* 10b - Hash*, XOR of address bits [20:16, 6]
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* 10b - Hash*, XOR of address bits [20:16, 6]
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* 11b - Hash*, XOR of address bits [20:16, 9]
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* 11b - Hash*, XOR of address bits [20:16, 9]
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*/
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*/
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break;
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}
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}
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return val;
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return val;
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