mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board

This patch adds initial support for Alderlake Intel Pre-CEP
board called shadowmountain.

BUG=b:175808146
TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max

Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/intel/shadowmountain/Kconfig

@@ -0,0 +1,25 @@
+if BOARD_INTEL_SHADOWMOUNTAIN
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+	select HAVE_ACPI_TABLES
+	select SOC_INTEL_ALDERLAKE
+
+config DEVICETREE
+	string
+	default "variants/baseboard/devicetree.cb"
+
+config MAINBOARD_DIR
+	string
+	default "intel/shadowmountain"
+
+config MAINBOARD_FAMILY
+	string
+	default "Intel_shadowmountain"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "shadowmountain"
+
+endif # BOARD_INTEL_SHADOWMOUNTAIN

src/mainboard/intel/shadowmountain/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_INTEL_SHADOWMOUNTAIN
+	bool "shadowmountain"

src/mainboard/intel/shadowmountain/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Alderlake Pre-CEP
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/intel/shadowmountain/dsdt.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+}

src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb

@@ -0,0 +1,5 @@
+chip soc/intel/alderlake
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+end