diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1ec207646b..2bfb07c9a1 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -65,6 +65,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_IRQ
 	select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16
 	select SOC_INTEL_COMMON_BLOCK_MEMINIT
+	select SOC_INTEL_COMMON_BLOCK_OC_WDT
 	select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
 	select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index dfe3b323aa..a674b0acc6 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -9,6 +9,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/early_graphics.h>
+#include <intelblocks/oc_wdt.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
@@ -166,6 +167,8 @@ void mainboard_romstage_entry(void)
 	struct chipset_power_state *ps = pmc_get_power_state();
 	bool s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 
+	setup_oc_wdt();
+
 	/* Initialize HECI interface */
 	cse_init(HECI1_BASE_ADDRESS);