vendorcode/intel: Add initial FSP headers for Cannonlake
Intial FSP headers with FSP version 1.5.30 Change-Id: I4471c6aa40ff23179b033a873aec1887b8b4370e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov
Aaron Durbin
parent
9cd59312f8
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ce1b28f966
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/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C4E43 /* 'CNLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E43 /* 'CNLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C4E43 /* 'CNLUPD_S' */
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#pragma pack()
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#endif
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/** @file
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This file contains definitions required for creation of
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Memory S3 Save data, Memory Info data and Memory Platform
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data hobs.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2017 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _MEM_INFO_HOB_H_
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#define _MEM_INFO_HOB_H_
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#pragma pack (push, 1)
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extern EFI_GUID gSiMemoryS3DataGuid;
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extern EFI_GUID gSiMemoryInfoDataGuid;
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extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define MAX_NODE 1
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#define MAX_CH 2
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#define MAX_DIMM 2
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///
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/// Host reset states from MRC.
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///
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#define WARM_BOOT 2
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#define R_MC_CHNL_RANK_PRESENT 0x7C
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#define B_RANK0_PRS BIT0
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#define B_RANK1_PRS BIT1
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#define B_RANK2_PRS BIT4
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#define B_RANK3_PRS BIT5
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// @todo remove and use the MdePkg\Include\Pi\PiHob.h
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#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
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#ifndef __HOB__H__
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typedef struct _EFI_HOB_GENERIC_HEADER {
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UINT16 HobType;
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UINT16 HobLength;
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UINT32 Reserved;
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} EFI_HOB_GENERIC_HEADER;
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typedef struct _EFI_HOB_GUID_TYPE {
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EFI_HOB_GENERIC_HEADER Header;
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EFI_GUID Name;
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///
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/// Guid specific data goes here
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///
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} EFI_HOB_GUID_TYPE;
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#endif
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#endif
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///
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/// Defines taken from MRC so avoid having to include MrcInterface.h
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///
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//
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// Matches MAX_SPD_SAVE define in MRC
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//
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#ifndef MAX_SPD_SAVE
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#define MAX_SPD_SAVE 29
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#endif
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//
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// MRC version description.
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//
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typedef struct {
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UINT8 Major; ///< Major version number
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UINT8 Minor; ///< Minor version number
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UINT8 Rev; ///< Revision number
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UINT8 Build; ///< Build number
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} SiMrcVersion;
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//
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// Matches MrcDimmSts enum in MRC
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//
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#ifndef DIMM_ENABLED
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#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
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#endif
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#ifndef DIMM_DISABLED
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#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
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#endif
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#ifndef DIMM_PRESENT
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#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
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#endif
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#ifndef DIMM_NOT_PRESENT
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#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
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#endif
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//
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// Matches MrcBootMode enum in MRC
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//
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#ifndef bmCold
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#define bmCold 0 // Cold boot
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#endif
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#ifndef bmWarm
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#define bmWarm 1 // Warm boot
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#endif
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#ifndef bmS3
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#define bmS3 2 // S3 resume
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#endif
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#ifndef bmFast
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#define bmFast 3 // Fast boot
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#endif
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//
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// Matches MrcDdrType enum in MRC
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//
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#ifndef MRC_DDR_TYPE_DDR4
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#define MRC_DDR_TYPE_DDR4 0
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#endif
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#ifndef MRC_DDR_TYPE_DDR3
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#define MRC_DDR_TYPE_DDR3 1
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#endif
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#ifndef MRC_DDR_TYPE_LPDDR3
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#define MRC_DDR_TYPE_LPDDR3 2
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#endif
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 3
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#endif
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#define MAX_PROFILE_NUM 4 // number of memory profiles supported
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#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
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//
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// DIMM timings
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//
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typedef struct {
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UINT32 tCK; ///< Memory cycle time, in femtoseconds.
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UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
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UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
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UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
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UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
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UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
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UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
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UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
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UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
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UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
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UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
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UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
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UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
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UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
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UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
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UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
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UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
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UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
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UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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} MRC_CH_TIMING;
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///
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/// Memory SMBIOS & OC Memory Data Hob
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///
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typedef struct {
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UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
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UINT8 DimmId;
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UINT32 DimmCapacity; ///< DIMM size in MBytes.
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UINT16 MfgId;
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UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
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UINT8 RankInDimm; ///< The number of ranks in this DIMM.
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UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
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UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
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UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
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UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
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} DIMM_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this channel should be used.
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UINT8 ChannelId;
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UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
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MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
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DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
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} CHANNEL_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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} CONTROLLER_INFO;
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typedef struct {
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UINT8 Revision;
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UINT16 DataWidth; ///< Data width, in bits, of this memory device
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/** As defined in SMBIOS 3.0 spec
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Section 7.18.2 and Table 75
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**/
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UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
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UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
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UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
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/** As defined in SMBIOS 3.0 spec
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Section 7.17.3 and Table 72
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**/
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UINT8 ErrorCorrectionType;
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SiMrcVersion Version;
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BOOLEAN EccSupport;
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UINT8 MemoryProfile;
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UINT32 TotalPhysicalMemorySize;
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UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
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UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
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UINT8 Ratio;
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UINT8 RefClk;
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UINT32 VddVoltage[MAX_PROFILE_NUM];
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CONTROLLER_INFO Controller[MAX_NODE];
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} MEMORY_INFO_DATA_HOB;
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/**
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Memory Platform Data Hob
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<b>Revision 1:</b>
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- Initial version.
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<b>Revision 2:</b>
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- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
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**/
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typedef struct {
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UINT8 Revision;
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UINT8 Reserved[3];
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UINT32 BootMode;
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UINT32 TsegSize;
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UINT32 TsegBase;
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UINT32 PrmrrSize;
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UINT32 PrmrrBase;
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UINT32 GttBase;
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UINT32 MmioSize;
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UINT32 PciEBaseAddress;
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#ifdef CPU_CFL
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UINT32 GdxcIotBase;
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UINT32 GdxcIotSize;
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UINT32 GdxcMotBase;
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UINT32 GdxcMotSize;
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#endif //CPU_CFL
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//
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// CPU:RestrictedBegin
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//
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UINT32 SharedMailboxBase;
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//
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// CPU:RestrictedEnd
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//
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} MEMORY_PLATFORM_DATA;
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType;
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MEMORY_PLATFORM_DATA Data;
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UINT8 *Buffer;
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} MEMORY_PLATFORM_DATA_HOB;
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#pragma pack (pop)
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#endif // _MEM_INFO_HOB_H_
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