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mb/compulab/intense_pc: Clean PCH and super-i/o config up 

The generic PCH code already enables a superset of LPC decoding. Move
UART setup to bootblock_mainboard_early_init() where it is expected.
Last but not least, remove an odd write to BUCs (RCBA+0x3414) and
beyond, as it's an 8-bit register and shouldn't be bluntly zeroed.

Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2019-11-17 00:42:57 +01:00 committed by Patrick Georgi
parent 8d6d3fa109
commit ce20697513
1 changed files with 4 additions and 21 deletions
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25
src/mainboard/compulab/intense_pc/early_init.c
View File

@ -23,27 +23,6 @@
#define SIO_PORT 0x164e #define SIO_PORT 0x164e
void mainboard_pch_lpc_setup(void)
{
pci_devfn_t dev = PCH_LPC_DEV;
/* Enable SuperIO */
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
#if CONFIG(DRIVERS_UART_8250IO)
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {
pci_write_config16(dev, LPC_EN,
lpc_config | COMA_LPC_EN);
}
#endif
}
void mainboard_late_rcba_config(void)
{
RCBA32(0x3414) = 0x00000000;
}
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, { 1, 1, 0 },
{ 1, 1, 0 }, { 1, 1, 0 },
@ -66,6 +45,10 @@ void bootblock_mainboard_early_init(void)
const u16 port = SIO_PORT; const u16 port = SIO_PORT;
const u16 runtime_port = 0x180; const u16 runtime_port = 0x180;
/* Enable COM1 if requested */
if (CONFIG(DRIVERS_UART_8250IO))
sio1007_enable_uart_at(port);
/* Turn on configuration mode. */ /* Turn on configuration mode. */
outb(0x55, port); outb(0x55, port);