mb/compulab/intense_pc: Clean PCH and super-i/o config up
The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's an 8-bit register and shouldn't be bluntly zeroed. Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -23,27 +23,6 @@
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#define SIO_PORT 0x164e
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void mainboard_pch_lpc_setup(void)
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{
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pci_devfn_t dev = PCH_LPC_DEV;
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/* Enable SuperIO */
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u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN;
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pci_write_config16(dev, LPC_EN, lpc_config);
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#if CONFIG(DRIVERS_UART_8250IO)
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/* Enable COM1 */
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if (sio1007_enable_uart_at(SIO_PORT)) {
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pci_write_config16(dev, LPC_EN,
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lpc_config | COMA_LPC_EN);
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}
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#endif
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}
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void mainboard_late_rcba_config(void)
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{
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RCBA32(0x3414) = 0x00000000;
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 1, 0 },
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{ 1, 1, 0 },
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@ -66,6 +45,10 @@ void bootblock_mainboard_early_init(void)
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const u16 port = SIO_PORT;
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const u16 runtime_port = 0x180;
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/* Enable COM1 if requested */
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if (CONFIG(DRIVERS_UART_8250IO))
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sio1007_enable_uart_at(port);
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/* Turn on configuration mode. */
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outb(0x55, port);
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