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soc/intel/skylake: Add option to skip coreboot MP init 

This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.

Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init

Default coreboot does MP initialization.

Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2018-06-04 10:05:07 +05:30
parent a0ad6e7873
commit ce23d4c6f1
21 changed files with 10 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/chell/devicetree.cb
View File

@ -48,7 +48,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/eve/devicetree.cb
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@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/fizz/devicetree.cb
View File

@ -79,7 +79,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/glados/devicetree.cb
View File

@ -48,7 +48,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/lars/devicetree.cb
View File

@ -36,7 +36,6 @@ chip soc/intel/skylake
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
register "PmTimerDisabled" = "1"
register "pirqa_routing" = "PCH_IRQ11"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -50,7 +50,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

2
src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
View File

@ -131,8 +131,6 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
register "FspSkipMpInit" = "1"
# Enable Root ports.
# PCIE Port 1 x4 -> SLOT1
register "PcieRpEnable[0]" = "1"

2
src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
View File

@ -132,8 +132,6 @@ chip soc/intel/skylake
.voltage_limit = 0x0 \
}"
register "FspSkipMpInit" = "1"
# Enable Root ports.
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"

2
src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
View File

@ -128,8 +128,6 @@ chip soc/intel/skylake
.voltage_limit = 0x0 \
}"
register "FspSkipMpInit" = "1"
# Enable Root port.
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"

2
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -141,8 +141,6 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
register "FspSkipMpInit" = "1"
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"

3
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -142,7 +142,8 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
register "FspSkipMpInit" = "0"
# Skip coreboot MP Init
register "use_fsp_mp_init" = "1"
# Enable x1 slot
register "PcieRpEnable[7]" = "1"

1
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
View File

@ -62,7 +62,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

1
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
View File

@ -62,7 +62,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

2
src/soc/intel/skylake/chip.c
View File

@ -171,7 +171,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SerialIrqConfigStartFramePulse =
config->SerialIrqConfigStartFramePulse;
params->SkipMpInit = config->FspSkipMpInit;
params->SkipMpInit = !config->use_fsp_mp_init;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];

7
src/soc/intel/skylake/chip.h
View File

@ -434,7 +434,12 @@ struct soc_intel_skylake_config {
SERIAL_IRQ_FRAME_PULSE_8CLK = 2,
} SerialIrqConfigStartFramePulse;
u8 FspSkipMpInit;
/*
* Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
*/
u8 use_fsp_mp_init;
/*
* VrConfig Settings for 5 domains

2
src/soc/intel/skylake/chip_fsp20.c
View File

@ -387,7 +387,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
params->PchSirqMode = config->SerialIrqConfigSirqMode;
params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit;
params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];