soc/intel/skylake: Add option to skip coreboot MP init

This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.

Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init

Default coreboot does MP initialization.

Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/chell/devicetree.cb

@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/eve/devicetree.cb

@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/fizz/devicetree.cb

@@ -79,7 +79,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/glados/devicetree.cb

@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/lars/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "FspSkipMpInit" = "1"
 	register "PmTimerDisabled" = "1"
 
 	register "pirqa_routing" = "PCH_IRQ11"

src/mainboard/google/poppy/variants/atlas/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/poppy/variants/nami/devicetree.cb

@@ -50,7 +50,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/poppy/variants/nocturne/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb

@@ -131,8 +131,6 @@ chip soc/intel/skylake
 		.voltage_limit = 0x5F0 \
 	}"
 
-	register "FspSkipMpInit" = "1"
-
 	# Enable Root ports.
 	# PCIE Port 1 x4 -> SLOT1
 	register "PcieRpEnable[0]" = "1"

src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb

@@ -132,8 +132,6 @@ chip soc/intel/skylake
 		.voltage_limit = 0x0 \
 	}"
 
-	register "FspSkipMpInit" = "1"
-
 	# Enable Root ports.
 	register "PcieRpEnable[2]" = "1"
 	register "PcieRpEnable[3]" = "1"

src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb

@@ -128,8 +128,6 @@ chip soc/intel/skylake
 		.voltage_limit = 0x0 \
 	}"
 
-	register "FspSkipMpInit" = "1"
-
 	# Enable Root port.
 	register "PcieRpEnable[3]" = "1"
 	register "PcieRpEnable[4]" = "1"

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -141,8 +141,6 @@ chip soc/intel/skylake
 		.voltage_limit = 0x5F0 \
 	}"
 
-	register "FspSkipMpInit" = "1"
-
 	# Enable Root port 1 and 5.
 	register "PcieRpEnable[0]" = "1"
 	register "PcieRpEnable[4]" = "1"

src/mainboard/intel/saddlebrook/devicetree.cb

@@ -142,7 +142,8 @@ chip soc/intel/skylake
 		.voltage_limit = 0x5F0 \
 	}"
 
-	register "FspSkipMpInit" = "0"
+	# Skip coreboot MP Init
+	register "use_fsp_mp_init" = "1"
 
 	# Enable x1 slot
 	register "PcieRpEnable[7]" = "1"

src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb

@@ -62,7 +62,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb

@@ -62,7 +62,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
-	register "FspSkipMpInit" = "1"
 	register "SaGv" = "3"
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms

src/soc/intel/skylake/chip.c

@@ -171,7 +171,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->SerialIrqConfigStartFramePulse =
 		config->SerialIrqConfigStartFramePulse;
 
-	params->SkipMpInit = config->FspSkipMpInit;
+	params->SkipMpInit = !config->use_fsp_mp_init;
 
 	for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
 		params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];

src/soc/intel/skylake/chip.h

@@ -434,7 +434,12 @@ struct soc_intel_skylake_config {
 		SERIAL_IRQ_FRAME_PULSE_8CLK = 2,
 	} SerialIrqConfigStartFramePulse;
 
-	u8 FspSkipMpInit;
+	/*
+	 * Option for mainboard to skip coreboot MP initialization
+	 * 0 = Make use of coreboot MP Init
+	 * 1 = Make use of FSP MP Init
+	 */
+	u8 use_fsp_mp_init;
 
 	/*
 	 * VrConfig Settings for 5 domains

src/soc/intel/skylake/chip_fsp20.c

@@ -387,7 +387,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
 	params->PchSirqMode = config->SerialIrqConfigSirqMode;
 
-	params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit;
+	params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init;
 
 	for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
 		params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];