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mb/google/sarien: leave gpio pads unlocks during fsp 

The FSP will lock down the configuration of GPP_A12, which
makes the configuration of the GPIO pin on warm reset not
work correctly.

This is only needed for the Arcada variant since it is the only variant
that uses ISH.

BRANCH=sarien
BUG=b:132719369
TEST=ISH_GP6 now works on warm resets on arcarda

Change-Id: Icb3bae2c48eee053189f1a878f5975c6afe51c71
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32831
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jett Rink 2019-05-15 13:40:05 -06:00 committed by Duncan Laurie
parent f42344a389
commit ce2c1cb742
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -26,6 +26,7 @@ chip soc/intel/cannonlake
register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpS4MinAssert" = "4" # 4s
register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s register "PchPmSlpAMinAssert" = "4" # 2s
register "PchUnlockGpioPads" = "1"
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"
register "psys_pmax" = "140" register "psys_pmax" = "140"