mb/purism/librem_cnl: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
This commit is contained in:
Felix Singer
Felix Singer
parent
185ff285f6
commit
ce391cd426
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@ -44,58 +44,58 @@ chip soc/intel/cannonlake
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal device
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device ref system_agent on end
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device ref igpu on end
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device ref dptf on
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on end # USB xHC
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 off end # PCI Express Port 13
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on end # LPC Bridge
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device pci 1f.1 off end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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device ref thermal on end
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device ref ish off end
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device ref xhci on end
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device ref xdci off end
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device ref i2c0 off end
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device ref i2c1 off end
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device ref i2c2 off end
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device ref i2c3 off end
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device ref heci1 off end
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device ref heci2 off end
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device ref csme_ider off end
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device ref csme_ktr off end
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device ref heci3 off end
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device ref heci4 off end
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device ref sata on end
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device ref i2c4 off end
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device ref i2c5 off end
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device ref uart2 off end
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device ref emmc off end
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device ref pcie_rp1 off end
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device ref pcie_rp2 off end
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device ref pcie_rp3 off end
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device ref pcie_rp4 off end
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device ref pcie_rp5 off end
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device ref pcie_rp6 off end
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device ref pcie_rp7 off end
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device ref pcie_rp8 off end
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device ref pcie_rp9 off end
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device ref pcie_rp10 off end
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device ref pcie_rp11 off end
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device ref pcie_rp12 off end
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device ref pcie_rp13 off end
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device ref pcie_rp14 off end
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device ref pcie_rp15 off end
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device ref pcie_rp16 off end
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device ref uart0 off end
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device ref uart1 off end
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device ref gspi0 off end
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device ref gspi1 off end
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device ref lpc_espi on end
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device ref p2sb off end
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device ref pmc hidden end
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device ref hda on
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register "PchHdaAudioLinkHda" = "1"
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end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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device ref smbus on end
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device ref fast_spi on end
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device ref gbe off end
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end
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end
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@ -24,7 +24,7 @@ chip soc/intel/cannonlake
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# Actual device tree
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device domain 0 on
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device pci 02.0 on # Integrated Graphics Device
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device ref igpu on
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register "gfx" = "GMA_DEFAULT_PANEL(0)"
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register "panel_cfg" = "{
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.up_delay_ms = 200,
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@ -35,7 +35,7 @@ chip soc/intel/cannonlake
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.backlight_off_delay_ms = 1,
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}"
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end
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device pci 14.0 on # USB xHCI
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device ref xhci on
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chip drivers/usb/acpi
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device usb 0.0 on
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chip drivers/usb/acpi
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@ -131,8 +131,8 @@ chip soc/intel/cannonlake
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 15.0 on # I2C #0
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device ref xdci off end
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device ref i2c0 on
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chip drivers/i2c/hid
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register "generic.hid" = ""HTIX5288""
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register "generic.name" = ""TPD0""
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@ -142,7 +142,7 @@ chip soc/intel/cannonlake
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device i2c 2c on end
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end
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end
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device pci 17.0 on # SATA
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device ref sata on
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register "satapwroptimize" = "1"
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register "SataSalpSupport" = "1"
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# Port 2 (M.2 / inner)
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@ -152,7 +152,7 @@ chip soc/intel/cannonlake
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[2]" = "1"
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end
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device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN)
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device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN)
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register "PcieRpEnable[6]" = "1"
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register "PcieRpSlotImplemented[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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@ -161,13 +161,13 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[2]" = "2"
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
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end
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device pci 1c.7 on # PCI Express Port 8
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device ref pcie_rp8 on
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device pci 00.0 on end # x1 (LAN)
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register "PcieRpEnable[7]" = "1"
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register "PcieClkSrcUsage[3]" = "7"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device pci 1d.0 on # PCI Express Port 9 -- x4 M.2/M 2280 (NVMe)
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device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpSlotImplemented[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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@ -175,7 +175,7 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[0]" = "0"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
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device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
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register "PcieRpEnable[12]" = "1"
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register "PcieRpSlotImplemented[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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@ -183,7 +183,7 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[1]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device pci 1f.0 on # LPC Bridge
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device ref lpc_espi on
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# LPC configuration from lspci -s 1f.0 -xxx
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# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
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register "gen1_dec" = "0x00040069"
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@ -20,7 +20,7 @@ chip soc/intel/cannonlake
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# Actual device tree
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device domain 0 on
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device pci 14.0 on # USB xHCI
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device ref xhci on
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chip drivers/usb/acpi
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device usb 0.0 on
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chip drivers/usb/acpi
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@ -123,12 +123,12 @@ chip soc/intel/cannonlake
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
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end
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device pci 17.0 on # SATA
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device ref sata on
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register "SataPortsEnable[0]" = "1" # 2.5"
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register "SataPortsEnable[2]" = "1" # m.2
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register "satapwroptimize" = "1"
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end
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device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN)
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device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN)
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register "PcieRpSlotImplemented[7]" = "1"
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register "PcieRpEnable[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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@ -136,13 +136,13 @@ chip soc/intel/cannonlake
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register "PcieClkSrcUsage[2]" = "0x80"
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
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end
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device pci 1d.1 on # PCI Express Port 10
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device ref pcie_rp10 on
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device pci 00.0 on end # x1 (LAN)
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register "PcieRpEnable[9]" = "1"
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register "PcieClkSrcUsage[3]" = "9"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
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device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
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register "PcieRpSlotImplemented[12]" = "1"
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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@ -150,7 +150,7 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[1]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device pci 1f.0 on # LPC Bridge
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device ref lpc_espi on
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chip superio/ite/it8528e
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device pnp 2e.1 on # UART1
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io 0x60 = 0x3F8
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