From ce39ba97bc1906e7fbfec09312fcfec2919cf03e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sat, 4 Jan 2020 16:15:50 +0200
Subject: [PATCH] drivers/pc80/rtc: Reorganize prototypes
MIME-Version: 1.0
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Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/arch/x86/cpu.c               |  1 +
 src/arch/x86/post.c              |  1 +
 src/device/device.c              |  1 +
 src/drivers/elog/elog.c          |  4 +---
 src/drivers/pc80/rtc/post.c      |  1 +
 src/include/console/console.h    | 26 +++-----------------------
 src/include/pc80/mc146818rtc.h   |  1 -
 src/include/post.h               | 28 ++++++++++++++++++++++++++++
 src/lib/bootblock.c              |  2 +-
 src/soc/intel/xeon_sp/skx/chip.c |  1 +
 10 files changed, 38 insertions(+), 28 deletions(-)
 create mode 100644 src/include/post.h

diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 8f8fdc1fd0..1ee8fb32c3 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -5,6 +5,7 @@
 #include <boot/coreboot_tables.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <post.h>
 #include <string.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/arch/x86/post.c b/src/arch/x86/post.c
index 0aaf9b7190..ec185c791e 100644
--- a/src/arch/x86/post.c
+++ b/src/arch/x86/post.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+#include <post.h>
 #include <stdint.h>
 #include <console/console.h>
 #include <arch/io.h>
diff --git a/src/device/device.c b/src/device/device.c
index cc1b37df1b..a5d223b1c0 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -9,6 +9,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <post.h>
 #include <stdlib.h>
 #include <string.h>
 #include <smp/spinlock.h>
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 1d4b1351b5..ab86f387cc 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -7,14 +7,12 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#if CONFIG(ARCH_X86)
-#include <pc80/mc146818rtc.h>
-#endif
 #include <bcd.h>
 #include <boot_device.h>
 #include <commonlib/region.h>
 #include <fmap.h>
 #include <lib.h>
+#include <post.h>
 #include <rtc.h>
 #include <smbios.h>
 #include <stdint.h>
diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c
index f993b96b2c..842deb71f6 100644
--- a/src/drivers/pc80/rtc/post.c
+++ b/src/drivers/pc80/rtc/post.c
@@ -2,6 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <stdint.h>
+#include <post.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 95c0e7fe1a..fdc48da73f 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -7,6 +7,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <console/post_codes.h>
+#include <console/vtxprintf.h>
 
 /* console.h is supposed to provide the log levels defined in here: */
 #include <commonlib/loglevel.h>
@@ -14,31 +15,10 @@
 #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER)
 #define RAM_SPEW  (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW  : BIOS_NEVER)
 
-#include <console/vtxprintf.h>
-
-struct device;
-
 void post_code(u8 value);
-void arch_post_code(u8 value);
-void cmos_post_code(u8 value);
-void cmos_post_extra(u32 value);
-void cmos_post_path(const struct device *dev);
-int cmos_post_previous_boot(u8 *code, u32 *extra);
-
-static inline void post_log_path(const struct device *dev)
-{
-	if (CONFIG(CMOS_POST) && dev)
-		cmos_post_path(dev);
-}
-
-static inline void post_log_clear(void)
-{
-	if (CONFIG(CMOS_POST))
-		cmos_post_extra(0);
-}
-
-/* this function is weak and can be overridden by a mainboard function. */
 void mainboard_post(u8 value);
+void arch_post_code(u8 value);
+
 void __noreturn die(const char *fmt, ...);
 #define die_with_post_code(value, fmt, ...) \
 	do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0)
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 353a09b416..c9e054b048 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -183,6 +183,5 @@ void cmos_set_checksum(int range_start, int range_end, int cks_loc);
 
 #endif /* CONFIG_ARCH_X86 */
 
-void cmos_post_init(void);
 
 #endif /*  PC80_MC146818RTC_H */
diff --git a/src/include/post.h b/src/include/post.h
new file mode 100644
index 0000000000..5c1e816ea7
--- /dev/null
+++ b/src/include/post.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef __POST_H__
+#define __POST_H__
+
+#include <stdint.h>
+#include <device/device.h>
+
+void cmos_post_init(void);
+void cmos_post_code(u8 value);
+void cmos_post_extra(u32 value);
+void cmos_post_path(const struct device *dev);
+int cmos_post_previous_boot(u8 *code, u32 *extra);
+
+static inline void post_log_path(const struct device *dev)
+{
+	if (CONFIG(CMOS_POST) && dev)
+		cmos_post_path(dev);
+}
+
+static inline void post_log_clear(void)
+{
+	if (CONFIG(CMOS_POST))
+		cmos_post_extra(0);
+}
+
+#endif
diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c
index 565d619a3e..b3d48604c3 100644
--- a/src/lib/bootblock.c
+++ b/src/lib/bootblock.c
@@ -6,7 +6,7 @@
 #include <console/console.h>
 #include <delay.h>
 #include <option.h>
-#include <pc80/mc146818rtc.h>
+#include <post.h>
 #include <program_loading.h>
 #include <symbols.h>
 #include <timestamp.h>
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index be452a05b6..9a9c45555c 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -15,6 +15,7 @@
 
 #include <cbfs.h>
 #include <assert.h>
+#include <post.h>
 #include <device/pci.h>
 #include <soc/acpi.h>
 #include <soc/ramstage.h>