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mb/google/cyan: fix RAM training on edgar variant 

Adapted from Chromium commit 5351dc0d
[Edgar: To set the RX ODT limit and dram geometry with RAMID detection]

Several cyan variants require memory init parameters be passed to FSP 
for handling of specific Micron modules; without these, RAM init will
fail when loading training data from the MRC cache, and boot will halt.
This was missed when I upstreamed edgar along with the other cyan
variants, so add the required memory init parameters for edgar as per
its source Chromium branch.

Test: build/boot on edgar board with affected Micron memory 
modules, verify boot successful with populated MRC cache.

Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31615
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2019-02-25 23:40:40 -06:00 committed by Patrick Georgi
parent 2201da3a8b
commit ce529b6318
2 changed files with 48 additions and 0 deletions
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1
src/mainboard/google/cyan/variants/edgar/Makefile.inc
View File

@ -14,6 +14,7 @@
## GNU General Public License for more details.
##
romstage-y += romstage.c
romstage-y += spd_util.c
ramstage-y += gpio.c

47
src/mainboard/google/cyan/variants/edgar/romstage.c Normal file
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@ -0,0 +1,47 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/romstage.h>
#include <baseboard/variants.h>
#include <mainboard/google/cyan/spd/spd_util.h>
void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
{
int ram_id = get_ramid();
/*
* RAMID = 5 - 4GiB Micron MT52L256M32D1PF-107
* RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107
*/
if (ram_id == 5 || ram_id == 7) {
/*
* For new micron part, it requires read/receive
* enable training before sending cmds to get MR8.
* To override dram geometry settings as below:
*
* PcdDramWidth = x32
* PcdDramDensity = 8Gb
* PcdDualRankDram = disable
*/
memory_params->PcdRxOdtLimitChannel0 = 1;
memory_params->PcdRxOdtLimitChannel1 = 1;
memory_params->PcdDisableAutoDetectDram = 1;
memory_params->PcdDramWidth = 2;
memory_params->PcdDramDensity = 3;
memory_params->PcdDualRankDram = 0;
}
}