soc/amd: factor out non-CAR romstage to common code

Since the romstage code is very similar between all AMD non-CAR SoCs,
factor out a common romstage implementation. All SoCs that select
SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so
this Kconfig option can be used to determine whether to make that call.
In the FSP case, amd_fsp_early_init gets called, while in the case of an
implementation that doesn't rely on an FSP to do the initialization,
cbmem_initialize_empty gets called to set up CBMEM which otherwise would
be done inside the FSP driver code. Since only some SoCs call
fch_disable_legacy_dma_io again in romstage right after
amd_fsp_early_init, introduce the new
SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the
SoCs can specify if this call is needed or not.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/soc/amd/cezanne/Kconfig

@@ -77,6 +77,7 @@ config SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
 	select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
 	select SOC_AMD_COMMON_BLOCK_XHCI
+	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select UDK_2017_BINDING
 	select USE_DDR4

src/soc/amd/cezanne/Makefile.inc

@@ -17,7 +17,6 @@ bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 
 romstage-y	+= fsp_m_params.c
-romstage-y	+= romstage.c
 
 ramstage-y	+= acpi.c
 ramstage-y	+= agesa_acpi.c

src/soc/amd/cezanne/romstage.c

@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
-	post_code(POSTCODE_ROMSTAGE_MAIN);
-
-	/* Snapshot chipset state prior to any FSP call */
-	fill_chipset_state();
-
-	amd_fsp_early_init();
-
-	/* Fixup settings FSP-M should not be changing */
-	fch_disable_legacy_dma_io();
-
-	memmap_stash_early_dram_usage();
-
-	run_ramstage();
-}

src/soc/amd/common/block/cpu/Kconfig

@@ -38,6 +38,12 @@ config ACPI_CPU_STRING
 	string
 	default "C%03X"
 
+config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
+	bool
+	help
+	  Disable the legacy DMA decodes again after the call into the
+	  reference code in romstage to fix up things.
+
 endif # SOC_AMD_COMMON_BLOCK_NONCAR
 
 config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H

src/soc/amd/common/block/cpu/noncar/Makefile.inc

@@ -8,6 +8,7 @@ bootblock-y += pre_c.S
 bootblock-y += write_resume_eip.c
 bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock_measure.c
 romstage-y += memmap.c
+romstage-y += romstage.c
 ramstage-y += cpu.c
 romstage-y += cpu.c
 ramstage-y += memmap.c

src/soc/amd/common/block/cpu/noncar/romstage.c

@@ -2,12 +2,11 @@
 
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/fsp.h>
+#include <amdblocks/post_codes.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
 #include <amdblocks/stb.h>
-#include <console/console.h>
+#include <cbmem.h>
-#include <cpu/cpu.h>
 #include <program_loading.h>
 #include <romstage_common.h>
 
@@ -18,13 +17,21 @@ void __noreturn romstage_main(void)
 	if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE))
 		write_stb_to_console();
 
-	/* Snapshot chipset state prior to any FSP call */
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE)) {
-	fill_chipset_state();
+		/* Snapshot chipset state prior to any reference code call. */
+		fill_chipset_state();
+	}
 
-	amd_fsp_early_init();
+	if (CONFIG(PLATFORM_USES_FSP2_0)) {
+		amd_fsp_early_init();
+	} else {
+		cbmem_initialize_empty();
+	}
 
-	/* Fixup settings FSP-M should not be changing */
+	if (CONFIG(SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP)) {
-	fch_disable_legacy_dma_io();
+		/* Fix up settings the reference code should not be changing */
+		fch_disable_legacy_dma_io();
+	}
 
 	memmap_stash_early_dram_usage();
 

src/soc/amd/genoa_poc/Makefile.inc

@@ -11,8 +11,6 @@ all-y		+= uart.c
 bootblock-y	+= early_fch.c
 bootblock-y	+= aoac.c
 
-romstage-y	+= romstage.c
-
 ramstage-y	+= acpi.c
 ramstage-y	+= aoac.c
 ramstage-y	+= chip.c

src/soc/amd/genoa_poc/romstage.c

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/post_codes.h>
-#include <amdblocks/memmap.h>
-#include <cbmem.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
-	post_code(POSTCODE_ROMSTAGE_MAIN);
-
-	cbmem_initialize_empty();
-	memmap_stash_early_dram_usage();
-	run_ramstage();
-}

src/soc/amd/glinda/Kconfig

@@ -78,6 +78,7 @@ config SOC_AMD_GLINDA
 	select SOC_AMD_COMMON_FSP_DMI_TABLES		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_FSP_PCI			# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
+	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select UDK_2017_BINDING
 	select USE_DDR5

src/soc/amd/glinda/Makefile.inc

@@ -22,7 +22,6 @@ bootblock-y	+= espi_util.c
 verstage-y	+= espi_util.c
 
 romstage-y	+= fsp_m_params.c
-romstage-y	+= romstage.c
 
 ramstage-y	+= acpi.c
 ramstage-y	+= agesa_acpi.c

src/soc/amd/glinda/romstage.c

@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
-	post_code(POSTCODE_ROMSTAGE_MAIN);
-
-	/* Snapshot chipset state prior to any FSP call */
-	fill_chipset_state();
-
-	amd_fsp_early_init();
-
-	/* Fixup settings FSP-M should not be changing */
-	fch_disable_legacy_dma_io();
-
-	memmap_stash_early_dram_usage();
-
-	run_ramstage();
-}

src/soc/amd/mendocino/Kconfig

@@ -84,6 +84,7 @@ config SOC_AMD_REMBRANDT_BASE
 	select SOC_AMD_COMMON_FSP_PCI
 	select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
 	select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
+	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select UDK_2017_BINDING
 	select USE_DDR5

src/soc/amd/mendocino/Makefile.inc

@@ -19,7 +19,6 @@ bootblock-y	+= espi_util.c
 verstage-y	+= espi_util.c
 
 romstage-y	+= fsp_m_params.c
-romstage-y	+= romstage.c
 
 ramstage-y	+= acpi.c
 ramstage-y	+= agesa_acpi.c

src/soc/amd/phoenix/Kconfig

@@ -72,6 +72,7 @@ config SOC_AMD_PHOENIX_BASE
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SOC_AMD_COMMON_BLOCK_UCODE
 	select SOC_AMD_COMMON_BLOCK_XHCI
+	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select USE_DDR5
 	select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK

src/soc/amd/phoenix/Makefile.inc

@@ -22,7 +22,6 @@ bootblock-y	+= espi_util.c
 verstage-y	+= espi_util.c
 
 romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c
-romstage-y	+= romstage.c
 romstage-y	+= soc_util.c
 
 ramstage-y	+= acpi.c

src/soc/amd/phoenix/romstage.c

@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
-	post_code(POSTCODE_ROMSTAGE_MAIN);
-
-	/* Snapshot chipset state prior to any FSP call */
-	fill_chipset_state();
-
-	amd_fsp_early_init();
-
-	/* Fixup settings FSP-M should not be changing */
-	fch_disable_legacy_dma_io();
-
-	memmap_stash_early_dram_usage();
-
-	run_ramstage();
-}

src/soc/amd/picasso/Makefile.inc

@@ -17,7 +17,6 @@ all_x86-y += uart.c
 bootblock-y += early_fch.c
 
 romstage-y += fsp_m_params.c
-romstage-y += romstage.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c

src/soc/amd/picasso/romstage.c

@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <commonlib/helpers.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-#include <types.h>
-
-void __noreturn romstage_main(void)
-{
-	post_code(POSTCODE_ROMSTAGE_MAIN);
-
-	/* Snapshot chipset state prior to any FSP call. */
-	fill_chipset_state();
-
-	amd_fsp_early_init();
-
-	memmap_stash_early_dram_usage();
-
-	run_ramstage();
-}