From ce6f1a53e9561c7a7ba35e0f21b0ba9ffc356efa Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Wed, 16 Oct 2019 13:47:15 +0800 Subject: [PATCH] mb/google/hatch: update DLL values for Kindred Update emmc DLL values for Kindred BUG=b:131401116 BRANCH=none TEST=Boot to OS 100 times on Kindred EVT Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/36076 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Shelley Chen --- .../google/hatch/variants/kindred/overridetree.cb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 272cbfb6ea..9d33fa96d0 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -61,7 +61,7 @@ chip soc/intel/cannonlake # Refer to EDS-Vol2-14.3.8. # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x0F10" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-14.3.9. @@ -69,7 +69,7 @@ chip soc/intel/cannonlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2F2D2D" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-14.3.10. @@ -77,7 +77,7 @@ chip soc/intel/cannonlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C121936" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-14.3.12. @@ -88,13 +88,13 @@ chip soc/intel/cannonlake # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1182D" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-14.3.11. # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on device pci 15.0 on