baytrail: allow ramstage_cache_location() usage in ramstage
To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5012 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -45,6 +45,8 @@ ramstage-y += lpss.c
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ramstage-y += pcie.c
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ramstage-y += sd.c
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ramstage-y += perf_power.c
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ramstage-y += stage_cache.c
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romstage-y += stage_cache.c
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# Remove as ramstage gets fleshed out
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ramstage-y += placeholders.c
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@ -355,19 +355,6 @@ static void *setup_stack_and_mttrs(void)
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return slot;
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}
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struct ramstage_cache *ramstage_cache_location(long *size)
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{
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char *smm_base;
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/* 1MiB cache size */
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const long cache_size = CONFIG_SMM_RESERVED_SIZE;
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/* Ramstage cache lives in TSEG region which is the definition of
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* cbmem_top(). */
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smm_base = cbmem_top();
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*size = cache_size;
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return (void *)&smm_base[smm_region_size() - cache_size];
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}
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void ramstage_cache_invalid(struct ramstage_cache *cache)
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{
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#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
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@ -0,0 +1,35 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cbmem.h>
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#include <ramstage_cache.h>
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#include <baytrail/smm.h>
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struct ramstage_cache *ramstage_cache_location(long *size)
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{
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char *smm_base;
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/* 1MiB cache size */
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const long cache_size = CONFIG_SMM_RESERVED_SIZE;
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/* Ramstage cache lives in TSEG region which is the definition of
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* cbmem_top(). */
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smm_base = cbmem_top();
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*size = cache_size;
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return (void *)&smm_base[smm_region_size() - cache_size];
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}
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