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PIC i8259: Move #defines and functions to i8259.h 

The PIC i8259.c file has a lot of #defines and function
definitions in it.  I am moving these to the i8259.h file
and also adding a few functions to update the PIC IRQ mask
register.  The PIC default configuration has all of its
interrupts masked off except for IRQ2.  IRQ2 is where
the Slave PIC is cascaded from the Master PIC.

Change-Id: I78d505358c29fadbc184137a09120863ea1d5c13
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5950
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Mike Loptien 2014-01-03 16:54:56 -07:00
parent f5a2d2607f
commit ce740c474c
2 changed files with 100 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
src/drivers/pc80/i8259.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -21,40 +22,44 @@
#include <pc80/i8259.h>
#include <console/console.h>
#define MASTER_PIC_ICW1 0x20
#define SLAVE_PIC_ICW1 0xa0
#define ICW_SELECT (1 << 4)
#define OCW_SELECT (0 << 4)
#define ADI (1 << 2)
#define SNGL (1 << 1)
#define IC4 (1 << 0)
/* Read the current PIC IRQ mask */
u16 pic_read_irq_mask(void)
{
u16 mask;
int i;
#define MASTER_PIC_ICW2 0x21
#define SLAVE_PIC_ICW2 0xa1
#define INT_VECTOR_MASTER 0x20
#define IRQ0 0x00
#define IRQ1 0x01
#define INT_VECTOR_SLAVE 0x28
#define IRQ8 0x00
#define IRQ9 0x01
mask = inb(MASTER_PIC_OCW1) | (inb(SLAVE_PIC_OCW1) << 8);
#define MASTER_PIC_ICW3 0x21
#define CASCADED_PIC (1 << 2)
printk(BIOS_DEBUG, "8259 PIC: OCW1 IRQ Mask: 0x%x\n", mask);
printk(BIOS_SPEW, "\tEnabled IRQs (0 = Unmasked, 1 = Masked off):\n"
"\t\tMaster\t\tSlave\n");
for(i = 0; i <= 7; i++) {
printk(BIOS_SPEW, "\t\tIRQ%X: %x\t\tIRQ%X: %x\n",
i, (mask >> i) & 1, i + 8, (mask >> (i + 8)) & 1);
}
return mask;
}
#define MASTER_PIC_ICW4 0x21
#define SLAVE_PIC_ICW4 0xa1
#define MICROPROCESSOR_MODE (1 << 0)
/*
* Write an IRQ mask to the PIC:
* IRQA is bit 0xA in the 16 bit bitmask (OCW1)
*/
void pic_write_irq_mask(u16 mask)
{
outb(mask, MASTER_PIC_OCW1);
outb(mask >> 8, SLAVE_PIC_OCW1);
}
#define SLAVE_PIC_ICW3 0xa1
#define SLAVE_ID 0x02
#define MASTER_PIC_OCW1 0x21
#define SLAVE_PIC_OCW1 0xa1
#define IRQ2 (1 << 2)
#define ALL_IRQS 0xff
#define ELCR1 0x4d0
#define ELCR2 0x4d1
/*
* The PIC IRQs default to masked off
* Allow specific IRQs to be enabled (1)
* or disabled by (0) the user
*/
void pic_irq_enable(u8 int_num, u8 mask)
{
pic_write_irq_mask(pic_read_irq_mask() & ~(mask << int_num));
pic_read_irq_mask();
}
void setup_i8259(void)
{
@ -113,14 +118,12 @@ void i8259_configure_irq_trigger(int int_num, int is_level_triggered)
{
u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
printk(BIOS_SPEW, "%s: current interrupts are 0x%x\n", __func__, int_bits);
if (is_level_triggered)
int_bits |= (1 << int_num);
else
int_bits &= ~(1 << int_num);
/* Write new values */
printk(BIOS_SPEW, "%s: try to set interrupts 0x%x\n", __func__, int_bits);
outb((u8)(int_bits & 0xff), ELCR1);
outb((u8)(int_bits >> 8), ELCR2);

66
src/include/pc80/i8259.h
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -20,10 +21,73 @@
#ifndef PC80_I8259_H
#define PC80_I8259_H
void setup_i8259(void);
/*
* IRQ numbers and common usage
* If an IRQ does not say it is 'Reserved'
* then it can be used by a device, though
* some systems may not adhere to this map.
*/
/* PIC IRQs */
#define IRQ_DIS 0x1F /* IRQ is disabled */
#define IRQ_0 0x00 /* Reserved - Timer IRQ */
#define IRQ_1 0x01 /* Keyboard controller */
#define IRQ_2 0x02 /* Reserved - Cascade to Slave PIC */
#define IRQ_3 0x03 /* Serial Port 2 & 4 */
#define IRQ_4 0x04 /* Serial Port 1 & 3 */
#define IRQ_5 0x05 /* Parallel Port 2 & 3 or Sound Card */
#define IRQ_6 0x06 /* Floppy Disk Controller */
#define IRQ_7 0x07 /* Parallel Port 1 */
#define IRQ_8 0x08 /* Reserved - RTC */
#define IRQ_9 0x09 /* Reserved - ACPI System Control Interrupt */
#define IRQ_10 0x0A /* Free or SCSI or NIC */
#define IRQ_11 0x0B /* Free or SCSI or NIC */
#define IRQ_12 0x0C /* PS/2 Mouse */
#define IRQ_13 0x0D /* Reserved - CPU Floating Point Unit */
#define IRQ_14 0x0E /* Primary ATA */
#define IRQ_15 0x0F /* Secondary ATA */
#define MASTER_PIC_ICW1 0x20
#define SLAVE_PIC_ICW1 0xa0
#define ICW_SELECT (1 << 4)
#define OCW_SELECT (0 << 4)
#define ADI (1 << 2)
#define SNGL (1 << 1)
#define IC4 (1 << 0)
#define MASTER_PIC_ICW2 0x21
#define SLAVE_PIC_ICW2 0xa1
#define INT_VECTOR_MASTER 0x20
#define IRQ0 0x00
#define IRQ1 0x01
#define INT_VECTOR_SLAVE 0x28
#define IRQ8 0x00
#define IRQ9 0x01
#define MASTER_PIC_ICW3 0x21
#define CASCADED_PIC (1 << 2)
#define MASTER_PIC_ICW4 0x21
#define SLAVE_PIC_ICW4 0xa1
#define MICROPROCESSOR_MODE (1 << 0)
#define SLAVE_PIC_ICW3 0xa1
#define SLAVE_ID 0x02
#define MASTER_PIC_OCW1 0x21
#define SLAVE_PIC_OCW1 0xa1
#define IRQ2 (1 << 2)
#define ALL_IRQS 0xff
#define ELCR1 0x4d0
#define ELCR2 0x4d1
#define IRQ_LEVEL_TRIGGERED 1
#define IRQ_EDGE_TRIGGERED 0
u16 pic_read_irq_mask(void);
void pic_write_irq_mask(u16 mask);
void pic_irq_enable(u8 int_num, u8 mask);
void setup_i8259(void);
void i8259_configure_irq_trigger(int int_num, int is_level_triggered);
#endif /* PC80_I8259_H */