mb/lowrisc: Remove the Nexys4DDR port
This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer
Ronald G. Minnich
parent
534b564345
commit
ce8763fb13
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@ -124,10 +124,8 @@ M: Ronald Minnich <rminnich@gmail.com>
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M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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S: Maintained
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S: Maintained
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F: src/arch/riscv/
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F: src/arch/riscv/
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F: src/soc/lowrisc
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F: src/soc/ucb/
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F: src/soc/ucb/
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F: src/mainboard/emulation/*-riscv/
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F: src/mainboard/emulation/*-riscv/
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F: src/mainboard/lowrisc
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POWER8 ARCHITECTURE
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POWER8 ARCHITECTURE
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M: Ronald Minnich <rminnich@gmail.com>
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M: Ronald Minnich <rminnich@gmail.com>
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@ -1,16 +0,0 @@
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if VENDOR_LOWRISC
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choice
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prompt "Mainboard model"
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source "src/mainboard/lowrisc/*/Kconfig.name"
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endchoice
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source "src/mainboard/lowrisc/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "lowrisc"
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endif # VENDOR_LOWRISC
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@ -1,2 +0,0 @@
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config VENDOR_LOWRISC
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bool "lowrisc"
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@ -1,37 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2016 Google Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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if BOARD_LOWRISC_NEXYS4DDR
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SOC_LOWRISC_LOWRISC
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select BOARD_ROMSIZE_KB_4096
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select DRIVERS_UART_8250MEM
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select BOOT_DEVICE_NOT_SPI_FLASH
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select UART_OVERRIDE_REFCLK
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config MAINBOARD_DIR
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string
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default lowrisc/nexys4ddr
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config MAINBOARD_PART_NUMBER
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string
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default "LOWRISC NEXYS4DDR"
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config MAX_CPUS
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int
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default 1
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endif # BOARD_LOWRISC_NEXYS4DDR
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@ -1,2 +0,0 @@
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config BOARD_LOWRISC_NEXYS4DDR
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bool "nexys4ddr"
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@ -1,25 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2016 Google Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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bootblock-y += uart.c
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bootblock-y += rom_media.c
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romstage-y += romstage.c
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romstage-y += uart.c
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romstage-y += rom_media.c
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ramstage-y += uart.c
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ramstage-y += rom_media.c
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bootblock-y += memlayout.ld
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romstage-y += memlayout.ld
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ramstage-y += memlayout.ld
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@ -1,3 +0,0 @@
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Board name: lowrisc nexys4ddr
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Category: eval
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Board URL: https://www.google.com/search?q=Tutorial+for+the+debug+preview+of+lowRISC&oq=Tutorial+for+the+debug+preview+of+lowRISC&btnI
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@ -1,20 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2016 Google, Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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chip soc/ucb/riscv
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device cpu_cluster 0 on end
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chip drivers/generic/generic # I2C0 controller
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device i2c 6 on end # Fake component for testing
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end
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end
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@ -1,35 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <device/device.h>
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#include <symbols.h>
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static void mainboard_enable(struct device *dev)
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{
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uintptr_t ram_base;
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size_t ram_size;
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/* FIXME: These values shouldn't necessarily be hardcoded */
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ram_base = 0x80000000;
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ram_size = 128 * MiB;
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ram_resource(dev, 0, ram_base / KiB, ram_size / KiB);
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cbmem_initialize_empty();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -1,31 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <memlayout.h>
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#include <arch/header.ld>
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#define START 0x80000000
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SECTIONS
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{
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DRAM_START(START)
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BOOTBLOCK(START, 64K)
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STACK(START + 8M, 64K)
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ROMSTAGE(START + 8M + 64K, 128K)
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PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
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/* hole at (START + 8M + 200K, 56K) */
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RAMSTAGE(START + 8M + 256K, 256K)
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}
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@ -1,30 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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* Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boot_device.h>
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#include <symbols.h>
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/*
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* _dram is the start of RAM. We currently need to load coreboot.rom into
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* RAM. The actual "rom" code on the FPGAs is in a block ram.
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*/
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static const struct mem_region_device boot_dev =
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MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE);
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const struct region_device *boot_device_ro(void)
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{
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return &boot_dev.rdev;
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}
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@ -1,23 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <program_loading.h>
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#include <console/console.h>
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void main(void)
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{
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console_init();
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run_ramstage();
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <console/uart.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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uintptr_t uart_platform_base(int idx)
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{
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return (uintptr_t) 0x42000000;
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}
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/* The clock which the UART is based on */
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unsigned int uart_platform_refclk(void)
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{
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return 25 * MHz;
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}
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@ -1,2 +0,0 @@
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# Load all chipsets
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source "src/soc/lowrisc/*/Kconfig"
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config SOC_LOWRISC_LOWRISC
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select ARCH_RISCV
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select ARCH_BOOTBLOCK_RISCV
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select ARCH_VERSTAGE_RISCV
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select ARCH_ROMSTAGE_RISCV
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select ARCH_RAMSTAGE_RISCV
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART_8250MEM_32
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select GENERIC_UDELAY
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select HAVE_MONOTONIC_TIMER
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select RISCV_USE_ARCH_TIMER
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bool
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default n
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if SOC_LOWRISC_LOWRISC
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config RISCV_ARCH
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string
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default "rv64imafd"
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config RISCV_ABI
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string
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default "lp64d"
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config RISCV_CODEMODEL
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string
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default "medany"
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endif
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ifeq ($(CONFIG_SOC_LOWRISC_LOWRISC),y)
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bootblock-y += mtime.c
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romstage-y += cbmem.c
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ramstage-y += cbmem.c
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ramstage-y += mtime.c
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endif
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@ -1,26 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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void *cbmem_top(void)
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{
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uintptr_t base;
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size_t size;
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/* FIXME: These values shouldn't necessarily be hardcoded */
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base = 0x80000000;
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size = 128 * MiB;
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return (void *)(base + size);
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}
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@ -349,7 +349,7 @@ get_log_dedupe "ARM" \
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get_log_dedupe "RISC-V" \
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get_log_dedupe "RISC-V" \
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"$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | grep -v 'payloads/\|drivers/\|vendorcode/\|console' ); do dirname "$codedir"; done | grep -v '^src$')" \
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"$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | grep -v 'payloads/\|drivers/\|vendorcode/\|console' ); do dirname "$codedir"; done | grep -v '^src$')" \
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"riscv\|risc-v\|lowrisc\|sifive"
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"riscv\|risc-v\|sifive"
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get_log_dedupe "MIPS" \
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get_log_dedupe "MIPS" \
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"$(for codedir in $(grep -rl "_MIPS" --include=Kconfig | \
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"$(for codedir in $(grep -rl "_MIPS" --include=Kconfig | \
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