x86/car: Replace reference of copy_and_run location

For cases with POSTCAR_STAGE=y this reference pulled
in the implementation of run_ramstage() which we would
not call.

Using _program results with the same region being marked
as WRPROT-cacheble.

Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>

src/cpu/amd/car/cache_as_ram.inc

@@ -380,7 +380,7 @@ fam15_skip_dram_mtrr_setup:
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
 	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
-	movl	$copy_and_run, %eax
+	movl	$_program, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr

src/cpu/intel/car/core2/cache_as_ram.S

@@ -150,7 +150,7 @@ addrsize_set_high:
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
 	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
-	movl	$copy_and_run, %eax
+	movl	$_program, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr

src/cpu/intel/car/p3/cache_as_ram.S

@@ -139,7 +139,7 @@ addrsize_set_high:
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
 	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
-	movl	$copy_and_run, %eax
+	movl	$_program, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr

src/cpu/intel/car/p4-netburst/cache_as_ram.S

@@ -322,7 +322,7 @@ no_msr_11e:
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
 	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
-	movl	$copy_and_run, %eax
+	movl	$_program, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr

src/cpu/via/car/cache_as_ram.inc

@@ -116,7 +116,7 @@ clear_fixed_var_mtrr_out:
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
 	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
-	movl	$copy_and_run, %eax
+	movl	$_program, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
@@ -207,7 +207,7 @@ clear_fixed_var_mtrr_out:
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
 	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
-	movl	$copy_and_run, %eax
+	movl	$_program, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr

src/soc/intel/broadwell/romstage/cache_as_ram.inc

@@ -136,7 +136,7 @@ clear_mtrrs:
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
 	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
-	movl    $copy_and_run, %eax
+	movl    $_program, %eax
 	andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr