sb/intel/i82801[ij]x: use (more) RCBA register names instead of magic numbers
Change-Id: I909d7dd4968aa2f76df00c03e603e8e82a4824c0 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -46,11 +46,12 @@ void i82801ix_dmi_setup(void)
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RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16);
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RCBA32(0x0088) = 0x00109000;
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RCBA16(0x01fc) = 0x060b;
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RCBA32(0x01f4) = 0x86000040;
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RCBA8 (0x0220) = 0x45;
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RCBA32(0x2024) &= ~(1 << 7);
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/* NB: other CIRs are handled in i82801ix_early_settings(). */
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RCBA32(RCBA_CIR1) = 0x00109000;
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RCBA16(RCBA_CIR3) = 0x060b;
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RCBA32(RCBA_CIR2) = 0x86000040;
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RCBA8(RCBA_BCR) = 0x45;
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RCBA32(RCBA_CIR6) &= ~(1 << 7);
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/* VC1 setup for isochronous transfers: */
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@ -38,15 +38,16 @@ static void i82801ix_enable_device(struct device *dev)
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static void i82801ix_early_settings(const config_t *const info)
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{
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/* Program FERR# as processor break event indicator. */
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RCBA32(0x3410) |= (1 << 6);
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/* BIOS must program... */
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RCBA32(0x3430) = (RCBA32(0x3430) & ~(0x3 << 0)) | (0x2 << 0);
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RCBA32(0x3418) |= (1 << 0);
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RCBA32(0x350c) = (RCBA32(0x350c) & ~(0x3 << 26)) | (0x2 << 26);
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RCBA32(0x2034) = (RCBA32(0x2034) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(0x0f20) = (RCBA32(0x0f20) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(0x1d40) |= (1 << 0);
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RCBA32(0x352c) |= (3 << 16);
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RCBA32(GCS) |= (1 << 6);
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/* BIOS must program...
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* NB: other CIRs are handled in i82801ix_dmi_setup(). */
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RCBA32(RCBA_CIR8) = (RCBA32(RCBA_CIR8) & ~(0x3 << 0)) | (0x2 << 0);
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RCBA32(RCBA_FD) |= (1 << 0);
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RCBA32(RCBA_CIR9) = (RCBA32(RCBA_CIR9) & ~(0x3 << 26)) | (0x2 << 26);
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RCBA32(RCBA_CIR7) = (RCBA32(RCBA_CIR7) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(RCBA_CIR13) = (RCBA32(RCBA_CIR13) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(RCBA_CIR5) |= (1 << 0);
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RCBA32(RCBA_CIR10) |= (3 << 16);
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}
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static void i82801ix_pcie_init(const config_t *const info)
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@ -156,20 +156,32 @@
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#define RCBA_V1CTL 0x0020
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#define RCBA_V1STS 0x0026
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#define RCBA_PAT 0x0030
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#define RCBA_CIR1 0x0088
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#define RCBA_ESD 0x0104
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#define RCBA_ULD 0x0110
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#define RCBA_ULBA 0x0118
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#define RCBA_LCAP 0x01a4
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#define RCBA_LCTL 0x01a8
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#define RCBA_LSTS 0x01aa
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#define RCBA_CIR2 0x01f4
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#define RCBA_CIR3 0x01fc
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#define RCBA_BCR 0x0220
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#define RCBA_DMIC 0x0234
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#define RCBA_RPFN 0x0238
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#define RCBA_CIR13 0x0f20
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#define RCBA_CIR5 0x1d40
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#define RCBA_DMC 0x2010
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#define RCBA_CIR6 0x2024
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#define RCBA_CIR7 0x2034
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#define RCBA_HPTC 0x3404
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#define GCS 0x3410
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#define RCBA_BUC 0x3414
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#define RCBA_FD 0x3418 /* Function Disable, see below. */
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#define RCBA_CG 0x341c
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#define RCBA_FDSW 0x3420
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#define RCBA_CIR8 0x3430
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#define RCBA_CIR9 0x350c
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#define RCBA_CIR10 0x352c
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#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
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#define BUC_LAND (1 << 5) /* LAN */
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@ -38,15 +38,15 @@ static void i82801jx_enable_device(struct device *dev)
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static void i82801jx_early_settings(const config_t *const info)
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{
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/* Program FERR# as processor break event indicator. */
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RCBA32(0x3410) |= (1 << 6);
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RCBA32(GCS) |= (1 << 6);
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/* BIOS must program... */
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RCBA32(0x3430) = (RCBA32(0x3430) & ~(0x3 << 0)) | (0x2 << 0);
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RCBA32(0x3418) |= (1 << 0);
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RCBA32(0x350c) = (RCBA32(0x350c) & ~(0x3 << 26)) | (0x2 << 26);
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RCBA32(0x2034) = (RCBA32(0x2034) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(0x0f20) = (RCBA32(0x0f20) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(0x1d40) |= (1 << 0);
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RCBA32(0x352c) |= (3 << 16);
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RCBA32(RCBA_CIR8) = (RCBA32(RCBA_CIR8) & ~(0x3 << 0)) | (0x2 << 0);
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RCBA32(RCBA_FD) |= (1 << 0);
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RCBA32(RCBA_CIR9) = (RCBA32(RCBA_CIR9) & ~(0x3 << 26)) | (0x2 << 26);
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RCBA32(RCBA_CIR7) = (RCBA32(RCBA_CIR7) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(RCBA_CIR13) = (RCBA32(RCBA_CIR13) & ~(0xf << 16)) | (0x5 << 16);
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RCBA32(RCBA_CIR5) |= (1 << 0);
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RCBA32(RCBA_CIR10) |= (3 << 16);
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}
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static void i82801jx_pcie_init(const config_t *const info)
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@ -149,21 +149,32 @@
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#define RCBA_V1CTL 0x0020
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#define RCBA_V1STS 0x0026
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#define RCBA_PAT 0x0030
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#define RCBA_CIR1 0x0088
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#define RCBA_ESD 0x0104
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#define RCBA_ULD 0x0110
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#define RCBA_ULBA 0x0118
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#define RCBA_LCAP 0x01a4
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#define RCBA_LCTL 0x01a8
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#define RCBA_LSTS 0x01aa
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#define RCBA_CIR2 0x01f4
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#define RCBA_CIR3 0x01fc
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#define RCBA_BCR 0x0220
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#define RCBA_DMIC 0x0234
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#define RCBA_RPFN 0x0238
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#define RCBA_CIR13 0x0f20
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#define RCBA_CIR5 0x1d40
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#define RCBA_DMC 0x2010
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#define RCBA_CIR6 0x2024
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#define RCBA_CIR7 0x2034
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#define RCBA_HPTC 0x3404
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#define GCS 0x3410
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#define RCBA_BUC 0x3414
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#define RCBA_FD 0x3418 /* Function Disable, see below. */
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#define RCBA_CG 0x341c
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#define RCBA_FDSW 0x3420
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#define RCBA_CIR8 0x3430
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#define RCBA_CIR9 0x350c
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#define RCBA_CIR10 0x352c
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#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
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#define D31IP 0x3100 /* 32bit */
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