diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 86366bfa2d..58656df8f7 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -67,7 +67,6 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select INTEL_GMA_OPREGION_2_1
 	select INTEL_TME
-	select MP_SERVICES_PPI_V2
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
@@ -397,6 +396,24 @@ config ACPI_ADL_IPU_ES_SUPPORT
 	help
 	  Enables ACPI entry to provide silicon type information to IPU kernel driver.
 
+choice
+	prompt "Multiprocessor (MP) Initialization configuration to use"
+	default USE_FSP_MP_INIT
+
+config USE_FSP_MP_INIT
+	bool "Use FSP MP init"
+	select MP_SERVICES_PPI_V2
+	help
+	  Upon selection, coreboot brings APs from reset and the FSP runs feature programming.
+
+config USE_COREBOOT_MP_INIT
+	bool "Use coreboot MP init"
+	select RELOAD_MICROCODE_PATCH
+	help
+	  Upon selection, coreboot performs MP Init.
+
+endchoice
+
 if STITCH_ME_BIN
 
 config CSE_BPDT_VERSION
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 36fd50de17..05f3997287 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -404,9 +404,17 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
 		}
 	}
 
-	/* Use coreboot MP PPI services if Kconfig is enabled */
-	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
+	if (CONFIG(USE_FSP_MP_INIT)) {
+		/*
+		 * Use FSP running MP PPI services to perform CPU feature programming
+		 * if Kconfig is enabled
+		 */
 		s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+	} else {
+		/* Use coreboot native driver to perform MP init by default */
+		s_cfg->CpuMpPpi = (uintptr_t)NULL;
+		s_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
+	}
 }
 
 static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,