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include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC 

Those registers are architectural MSR and this also gets them in line
with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the
definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are
ascending.

Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56235
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-07-12 23:46:21 +02:00
parent 78ab06ace9
commit ceb2fbb920
2 changed files with 4 additions and 4 deletions
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4
src/include/cpu/x86/msr.h
View File

@ -74,11 +74,11 @@
#define MCA_STATUS_LO_ERRCODE_EXT_SH 16
#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
#define IA32_MC0_ADDR 0x402
#define IA32_MC0_MISC 0x403
#define IA32_VMX_BASIC_MSR 0x480
#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
#define IA32_VMX_MISC_MSR 0x485
#define MC0_ADDR 0x402
#define MC0_MISC 0x403
#define MC0_CTL_MASK 0xC0010044
#define IA32_PM_ENABLE 0x770

4
src/soc/amd/stoneyridge/mca.c
View File

@ -169,10 +169,10 @@ void check_mca(void)
printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n",
i, mci.sts.hi, mci.sts.lo);
mci.addr = rdmsr(MC0_ADDR + (i * 4));
mci.addr = rdmsr(IA32_MC0_ADDR + (i * 4));
printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n",
i, mci.addr.hi, mci.addr.lo);
mci.misc = rdmsr(MC0_MISC + (i * 4));
mci.misc = rdmsr(IA32_MC0_MISC + (i * 4));
printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n",
i, mci.misc.hi, mci.misc.lo);
mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4));