soc/intel/icl: Rework on HECI1 disable configs

The only option to make HECI1 function disable on Ice Lake SoC
platform is using SBI under SMM mode. Hence, this patch makes
DISABLE_HECI1_AT_PRE_BOOT=y default and selects
`HECI_DISABLE_USING_SMM` config for Ice Lake.

Also, drop `HeciEnabled` from chip configuration and guard
heci_disable() using DISABLE_HECI1_AT_PRE_BOOT config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/icelake/Kconfig

@@ -61,9 +61,12 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select UDK_2017_BINDING
 	select DISPLAY_FSP_VERSION_INFO
-	select HECI_DISABLE_USING_SMM
 	select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
 
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y if MAINBOARD_HAS_CHROMEOS
+	select HECI_DISABLE_USING_SMM
+
 config DCACHE_RAM_BASE
 	default 0xfef00000
 

src/soc/intel/icelake/chip.h

@@ -134,10 +134,6 @@ struct soc_intel_icelake_config {
 
 	uint8_t Device4Enable;
 
-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
-
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
 

src/soc/intel/icelake/smihandler.c

@@ -16,11 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_icelake_config *config;
-
-	config = config_of_soc();
-
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
 		heci_disable();
 }