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emeraldlake2: Support native raminit. 

Change-Id: I808a739c91cb52782db46fd4897b6b913224d93f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13666
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Vladimir Serbinenko 2016-02-10 03:09:46 +01:00
parent a0f6abcada
commit cf0e9021da
2 changed files with 24 additions and 4 deletions
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4
src/mainboard/intel/emeraldlake2/Kconfig
View File

@ -13,10 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_INT15
#select MAINBOARD_HAS_CHROMEOS
config USE_NATIVE_RAMINIT
bool
default n
config CHROMEOS
#select CHROMEOS_VBNV_CMOS

24
src/mainboard/intel/emeraldlake2/romstage.c
View File

@ -29,6 +29,7 @@
#include <superio/smsc/sio1007/chip.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
@ -154,6 +155,29 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
*pei_data = pei_data_template;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */
{ 1, 0, 0 }, /* P0: Front port (OC0) */
{ 1, 0, 1 }, /* P1: Back port (OC1) */
{ 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, -1 }, /* P3: MMC (no OC) */
{ 1, 0, 2 }, /* P4: Front port (OC2) */
{ 0, 0, -1 }, /* P5: Empty */
{ 0, 0, -1 }, /* P6: Empty */
{ 0, 0, -1 }, /* P7: Empty */
{ 1, 0, 4 }, /* P8: Back port (OC4) */
{ 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
{ 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
{ 0, 0, -1 }, /* P11: Empty */
{ 1, 0, 6 }, /* P12: Back port (OC6) */
{ 1, 0, 5 }, /* P13: Back port (OC5) */
};
void mainboard_get_spd(spd_raw_data *spd) {
read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x52);
}
void mainboard_early_init(int s3resume)
{
}