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builds and should do the right things for sb for interrupt routing. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-04-25 19:57:39 +00:00
parent 1c2f49e74a
commit cf120d1a89
2 changed files with 22 additions and 10 deletions
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2
src/southbridge/amd/cs5536/Config.lb
View File

@ -1,4 +1,4 @@
#config chip.h
config chip.h
driver cs5536.o
#driver cs5536_pci.o
#driver cs5536_ide.o

30
src/southbridge/amd/cs5536/cs5536.c
View File

@ -5,7 +5,9 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include "cs5536.h"
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include "chip.h"
static void southbridge_init(struct device *dev)
{
@ -17,23 +19,25 @@ static void southbridge_enable(struct device *dev)
{
struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
msr_t msr;
struct device *gpiodev;
unsigned short gpiobase = MDD_GPIO;
/*
* struct device *gpiodev;
* unsigned short gpiobase = MDD_GPIO;
*/
printk_err("%s: dev is %p\n", __FUNCTION__, dev);
if (chip_info->lpc_serirq_enable) {
msr.lo = chip_info->lpc_serirq_enable;
if (sb->lpc_serirq_enable) {
msr.lo = sb->lpc_serirq_enable;
msr.hi = 0;
wrmsr(MDD_LPC_SIRQ, msr);
}
if (chip_info->lpc_irq) {
msr.lo = chip_info->lpc_irq;
if (sb->lpc_irq) {
msr.lo = sb->lpc_irq;
msr.hi = 0;
wrmsr(MDD_IRQM_LPC, msr);
}
if (chip_info->enable_gpio0_inta){
rdmsr(MDD_IRQM_ZHIGH, msr);
if (sb->enable_gpio0_inta){
msr = rdmsr(MDD_IRQM_ZHIGH);
msr.lo |= 0x10;
wrmsr(MDD_IRQM_ZHIGH, msr);
/* todo: look the device up. But we know that gpiobase is 0x6100 */
@ -69,3 +73,11 @@ static struct pci_driver cs5536_pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_CS5536_ISA
};
struct chip_operations southbridge_amd_cs5536_ops = {
CHIP_NAME("AMD cs5536")
/* This only called when this device is listed in the
* static device tree.
*/
.enable_dev = southbridge_enable,
};