From cf17cd81d3e7f098fdef8d3af6f167409e1b157e Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 23 Jul 2021 16:43:18 -0600 Subject: [PATCH] soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Julius Werner --- src/soc/amd/common/block/lpc/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index e775606910..76f4ec7ac3 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -16,6 +16,12 @@ config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA help Select this option to enable SPI DMA support. +# The LPC SPI DMA controller requires the destination buffers to be 64 byte +# aligned. +config CBFS_CACHE_ALIGN + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help