diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 4b33a3c58f..b3a9b00bc0 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -53,15 +53,10 @@
 
 static void lpc_common_init(device_t dev)
 {
-	u8 byte;
 	u32 dword;
 	struct resource *res;
 
 	/* I/O APIC initialization. */
-	byte = pci_read_config8(dev, 0x74);
-	byte |= (1 << 0);	/* Enable APIC. */
-	pci_write_config8(dev, 0x74, byte);
-
 	res = find_resource(dev, PCI_BASE_ADDRESS_1);  /* IOAPIC */
 	ASSERT(res != NULL);
 	setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
@@ -221,6 +216,7 @@ static void ck804_lpc_read_resources(device_t dev)
 
 static void ck804_lpc_set_resources(device_t dev)
 {
+	u8 byte;
 	struct resource *res;
 
 	pci_dev_set_resources(dev);
@@ -228,9 +224,15 @@ static void ck804_lpc_set_resources(device_t dev)
 	/* APIC */
 	res = find_resource(dev, PCI_BASE_ADDRESS_1);
 	if (res) {
+		byte = pci_read_config8(dev, 0x74);
+		byte |= (1 << 1);	/* enable access to PCI_BASE_ADDRESS_1 */
+		pci_write_config8(dev, 0x74, byte);
 		pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base);
 		res->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, res, "");
+		byte |= (1 << 0);	/* enable decode of IOAPIC space */
+		byte &= ~(1 << 1);	/* hide PCI_BASE_ADDRESS_1 */
+		pci_write_config8(dev, 0x74, byte);
 	}
 
 	/* HPET */