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cpu/intel/smm: Don't make assumptions on TSEG_SIZE 

Do not assume:
- TSEG is 8M
- IED_REGION_SIZE is set (not needed on older platforms).

Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27872
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-08-06 15:00:25 +02:00 committed by Patrick Georgi
parent e19d61b4e8
commit cf2941aec2
1 changed files with 21 additions and 10 deletions
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31
src/cpu/intel/smm/gen1/smmrelocate.c
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@ -16,6 +16,7 @@
/* SMM relocation with intention to work for i945-ivybridge. /* SMM relocation with intention to work for i945-ivybridge.
Right now used for sandybridge and ivybridge. */ Right now used for sandybridge and ivybridge. */
#include <assert.h>
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <device/device.h> #include <device/device.h>
@ -120,10 +121,15 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
* size * CPU num. */ * size * CPU num. */
save_state->smbase = relo_params->smram_base - save_state->smbase = relo_params->smram_base -
cpu * runtime->save_state_size; cpu * runtime->save_state_size;
save_state->iedbase = relo_params->ied_base; if (CONFIG_IED_REGION_SIZE != 0) {
save_state->iedbase = relo_params->ied_base;
printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
save_state->smbase, save_state->iedbase, save_state); save_state->smbase, save_state->iedbase, save_state);
} else {
printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n",
save_state->smbase, save_state);
}
/* Write SMRR MSRs based on indicated support. */ /* Write SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR); mtrr_cap = rdmsr(MTRR_CAP_MSR);
@ -144,16 +150,20 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
configuration value instead. */ configuration value instead. */
const u32 tseg_size = northbridge_get_tseg_size(); const u32 tseg_size = northbridge_get_tseg_size();
/* The SMRAM available to the handler is 4MiB
since the IEDRAM lives at TSEGMB + 4MiB. */
params->smram_base = tsegmb; params->smram_base = tsegmb;
params->smram_size = 4 << 20; params->smram_size = tseg_size;
params->ied_base = tsegmb + params->smram_size; if (CONFIG_IED_REGION_SIZE != 0) {
params->ied_size = tseg_size - params->smram_size; ASSERT(params->smram_size > CONFIG_IED_REGION_SIZE);
params->smram_size -= CONFIG_IED_REGION_SIZE;
params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE;
params->ied_size = CONFIG_IED_REGION_SIZE;
}
/* Adjust available SMM handler memory size. */ /* Adjust available SMM handler memory size. */
if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
params->smram_size -= CONFIG_SMM_RESERVED_SIZE; params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
}
if (IS_ALIGNED(tsegmb, tseg_size)) { if (IS_ALIGNED(tsegmb, tseg_size)) {
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
@ -259,7 +269,8 @@ static int cpu_smm_setup(void)
/* enable the SMM memory window */ /* enable the SMM memory window */
northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG); northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG);
setup_ied_area(&smm_reloc_params); if (CONFIG_IED_REGION_SIZE != 0)
setup_ied_area(&smm_reloc_params);
num_cpus = cpu_get_apic_id_map(apic_id_map); num_cpus = cpu_get_apic_id_map(apic_id_map);
if (num_cpus > CONFIG_MAX_CPUS) { if (num_cpus > CONFIG_MAX_CPUS) {