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src/mainboard/google/guybrush: update devicetree with USB settings 

All relevant USB phy settings can now be controlled via devicetree.
The given values are the AMD default ones.
For proper tuning procedure and values contact AMD.

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ie8d08bde54f8c0cb8202ba111b9c7a9bd33fa03e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Julian Schroeder 2021-05-21 14:56:00 -05:00 committed by Felix Held
parent d2f3308ad7
commit cf2c99f40c
1 changed files with 125 additions and 0 deletions
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125
src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
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@ -52,6 +52,131 @@ chip soc/amd/cezanne
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
register "usb_phy_custom" = "1"
register "usb_phy" = "{
.Usb2PhyPort[0] = {
.compdstune = 3,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 1,
.txpreemppulsetune = 0,
.txrisetune = 1,
.txvreftune = 6,
.txhsxvtune = 3,
.txrestune = 1,
},
.Usb2PhyPort[1] = {
.compdstune = 3,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 1,
.txpreemppulsetune = 0,
.txrisetune = 1,
.txvreftune = 6,
.txhsxvtune = 3,
.txrestune = 1,
},
.Usb2PhyPort[2] = {
.compdstune = 1,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 2,
.txpreemppulsetune = 0,
.txrisetune = 2,
.txvreftune = 3,
.txhsxvtune = 3,
.txrestune = 2,
},
.Usb2PhyPort[3] = {
.compdstune = 1,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 2,
.txpreemppulsetune = 0,
.txrisetune = 2,
.txvreftune = 3,
.txhsxvtune = 3,
.txrestune = 2,
},
.Usb2PhyPort[4] = {
.compdstune = 3,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 1,
.txpreemppulsetune = 0,
.txrisetune = 1,
.txvreftune = 6,
.txhsxvtune = 3,
.txrestune = 1,
},
.Usb2PhyPort[5] = {
.compdstune = 3,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 1,
.txpreemppulsetune = 0,
.txrisetune = 1,
.txvreftune = 6,
.txhsxvtune = 3,
.txrestune = 1,
},
.Usb2PhyPort[6] = {
.compdstune = 1,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 2,
.txpreemppulsetune = 0,
.txrisetune = 2,
.txvreftune = 3,
.txhsxvtune = 3,
.txrestune = 2,
},
.Usb2PhyPort[7] = {
.compdstune = 1,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 2,
.txpreemppulsetune = 0,
.txrisetune = 2,
.txvreftune = 3,
.txhsxvtune = 3,
.txrestune = 2,
},
.Usb3PhyPort[0] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
.Usb3PhyPort[1] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
.Usb3PhyPort[2] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
.Usb3PhyPort[3] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
.ComboPhyStaticConfig[0] = 0,
.ComboPhyStaticConfig[1] = 0,
.Version_Major = 0xd,
.Version_Minor = 0x4,
.TableLength = 100,
.BatteryChargerEnable = 0,
.PhyP3CpmP4Support = 0,
}"
device domain 0 on
device ref gpp_bridge_0 on
chip drivers/wifi/generic