soc/intel/common: Remove common chip config use_fsp_mp_init
This patch ensures to make use of common MP Init Kconfig to choose desire method to peform MP initialization for platform. Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SADDLEBROOK_USES_FSP1_1
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select HAVE_CMOS_DEFAULT
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select MAINBOARD_USES_IFD_GBE_REGION
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select USE_INTEL_FSP_MP_INIT
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config SADDLEBROOK_USES_FSP1_1
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bool "FSP driver 1.1"
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@ -140,11 +140,6 @@ chip soc/intel/skylake
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.voltage_limit = 0x5F0 \
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}"
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# Skip coreboot MP Init
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register "common_soc_config" = "{
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.use_fsp_mp_init = 1,
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}"
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# Enable x1 slot
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register "PcieRpEnable[7]" = "1"
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register "PcieRpClkReqSupport[7]" = "1"
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@ -733,7 +733,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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if (!CONFIG(SOC_INTEL_GLK))
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silconfig->MonitorMwaitEnable = 0;
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silconfig->SkipMpInit = !chip_get_fsp_mp_init();
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silconfig->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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/* Disable setting of EISS bit in FSP. */
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silconfig->SpiEiss = 0;
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@ -64,8 +64,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
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m_cfg->VmxEnable = 0;
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else
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m_cfg->VmxEnable = config->VmxEnable;
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#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
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m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
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m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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#endif
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/* Disable CPU Flex Ratio and SaGv in recovery mode */
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@ -32,18 +32,3 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void)
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return soc_config;
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}
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/*
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* This function will get MP Init config
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*
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* Return values:
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* 0 = Make use of coreboot MP Init
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* 1 = Make use of FSP MP Init
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*/
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int chip_get_fsp_mp_init(void)
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{
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const struct soc_intel_common_config *common_config;
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common_config = chip_get_common_soc_structure();
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return common_config->use_fsp_mp_init;
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}
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@ -133,7 +133,7 @@ static void init_cpus(void *unused)
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struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
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assert(dev != NULL);
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if (chip_get_fsp_mp_init())
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if (CONFIG(USE_INTEL_FSP_MP_INIT))
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return;
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microcode_patch = intel_microcode_find();
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@ -151,7 +151,7 @@ static void wrapper_x86_setup_mtrrs(void *unused)
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/* Ensure to re-program all MTRRs based on DRAM resource settings */
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static void post_cpus_init(void *unused)
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{
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if (chip_get_fsp_mp_init())
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if (CONFIG(USE_INTEL_FSP_MP_INIT))
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return;
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if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0)
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@ -33,24 +33,9 @@ struct soc_intel_common_config {
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int chipset_lockdown;
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struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
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/*
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* Option for mainboard to skip coreboot MP initialization
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* 0 = Make use of coreboot MP Init
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* 1 = Make use of FSP MP Init
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*/
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uint8_t use_fsp_mp_init;
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};
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/* This function to retrieve soc config structure required by common code */
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const struct soc_intel_common_config *chip_get_common_soc_structure(void);
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/*
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* This function will get MP Init config
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*
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* Return values:
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* 0 = Make use of coreboot MP Init
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* 1 = Make use of FSP MP Init
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*/
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int chip_get_fsp_mp_init(void);
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#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */
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@ -197,7 +197,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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params->SerialIrqConfigStartFramePulse =
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config->SerialIrqConfigStartFramePulse;
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params->SkipMpInit = !chip_get_fsp_mp_init();
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params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
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params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
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@ -27,6 +27,7 @@
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#include <intelblocks/chip.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/xdci.h>
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#include <intelpch/lockdown.h>
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#include <romstage_handoff.h>
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@ -422,7 +423,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
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params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
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params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
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params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
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params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
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