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mb/siemens/mc_ehl1: Disable L1 substates for PCIe root ports 

L1 substates of a PCIe link are meant to save some power when the link
is not active but have the drawback that the PCIe latency is increased
as PLLs are switched on and off as needed.

In order to get a better realtime performance, disable all substates for
every PCIe root port.

Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Werner Zeh 2021-07-23 12:50:12 +02:00 committed by Patrick Georgi
parent c2f85c6aaf
commit cf35fd3748
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
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@ -69,6 +69,14 @@ chip soc/intel/elkhartlake
register "PcieClkSrcClkReq[4]" = "0xFF"
register "PcieClkSrcClkReq[5]" = "0xFF"
# Disable all L1 substates for PCIe root ports
register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"