diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
index 93c46aed0d..3bf072131a 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
+++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
@@ -65,12 +65,10 @@ Scope(\_GPE) {	/* Start Scope GPE */
 
 	/*  GPIO0 or GEvent8 event  */
 	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Store("PCI bridge wake event", Debug)
+		/* Notify PCI bridges of wake event */
+		Notify(\_SB.PCI0.PBR4, 0x02)
+		Notify(\_SB.PCI0.PBR5, 0x02)
 	}
 
 	/*  Azalia SCI event  */
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 8b48476037..df0f8fd63b 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -386,6 +386,7 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = {
 SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
 	{GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
 	{GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
+	{GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
 	{SCI_MAP_OHCI_12_0, PME_GPE},
 	{SCI_MAP_OHCI_13_0, PME_GPE},
 	{SCI_MAP_XHCI_10_0, PME_GPE},
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h
index 8e51a774f0..95febb76d7 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h
@@ -12,6 +12,7 @@
 #define EC_SCI_GEVENT		3
 #define EC_LID_GEVENT		22
 #define EC_SMI_GEVENT		23
+#define PCIE_GEVENT		8
 
 /* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but
  * we make the distinction between GEVENT pin and SCI.
@@ -19,5 +20,6 @@
 #define EC_SCI_GPE 		EC_SCI_GEVENT
 #define EC_LID_GPE		EC_LID_GEVENT
 #define PME_GPE			0x0b
+#define PCIE_GPE		0x18
 
 #endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H   */