AMD Inagua: buildOpts.c: Adapt whitespace to coding style
Mainly replace spaces by tabs and format comments correctly.
Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was
unfortunately incomplete and also used spaces instead of tabs in
some cases.
Hopefully fix this once and for all to have a template for the
other boards.
[1] http://review.coreboot.org/547
Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2526
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Paul Menzel
Stefan Reinauer
parent
030902b774
commit
cf4ecfbe01
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@ -37,23 +37,23 @@
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#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
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/* Select the cpu family. */
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#define INSTALL_FAMILY_10_SUPPORT FALSE
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#define INSTALL_FAMILY_12_SUPPORT FALSE
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#define INSTALL_FAMILY_14_SUPPORT TRUE
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#define INSTALL_FAMILY_15_SUPPORT FALSE
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/* Select the cpu family. */
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#define INSTALL_FAMILY_10_SUPPORT FALSE
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#define INSTALL_FAMILY_12_SUPPORT FALSE
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#define INSTALL_FAMILY_14_SUPPORT TRUE
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#define INSTALL_FAMILY_15_SUPPORT FALSE
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/* Select the cpu socket type. */
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#define INSTALL_G34_SOCKET_SUPPORT FALSE
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#define INSTALL_C32_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
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#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
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#define INSTALL_FS1_SOCKET_SUPPORT FALSE
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#define INSTALL_FM1_SOCKET_SUPPORT FALSE
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#define INSTALL_FP1_SOCKET_SUPPORT FALSE
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#define INSTALL_FT1_SOCKET_SUPPORT TRUE
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#define INSTALL_AM3_SOCKET_SUPPORT FALSE
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/* Select the cpu socket type. */
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#define INSTALL_G34_SOCKET_SUPPORT FALSE
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#define INSTALL_C32_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
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#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
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#define INSTALL_FS1_SOCKET_SUPPORT FALSE
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#define INSTALL_FM1_SOCKET_SUPPORT FALSE
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#define INSTALL_FP1_SOCKET_SUPPORT FALSE
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#define INSTALL_FT1_SOCKET_SUPPORT TRUE
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#define INSTALL_AM3_SOCKET_SUPPORT FALSE
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/*
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* Agesa optional capabilities selection.
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@ -61,163 +61,163 @@
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* Comment out or mark TRUE those features you want to REMOVE from the build.
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*/
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#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
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#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
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#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
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#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
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#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
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#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
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#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
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#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
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#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
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#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
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#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
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//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
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#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
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#define BLDOPT_REMOVE_DQS_TRAINING FALSE
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#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
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#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
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#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
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#define BLDOPT_REMOVE_SRAT FALSE
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#define BLDOPT_REMOVE_SLIT FALSE
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#define BLDOPT_REMOVE_WHEA FALSE
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#define BLDOPT_REMOVE_DMI TRUE
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#define BLDOPT_REMOVE_HT_ASSIST TRUE
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#define BLDOPT_REMOVE_ATM_MODE TRUE
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//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
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//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
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#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
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//#define BLDOPT_REMOVE_C6_STATE TRUE
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#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
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#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
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#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
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//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
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#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
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#define BLDOPT_REMOVE_DQS_TRAINING FALSE
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#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
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#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
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#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
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#define BLDOPT_REMOVE_SRAT FALSE
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#define BLDOPT_REMOVE_SLIT FALSE
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#define BLDOPT_REMOVE_WHEA FALSE
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#define BLDOPT_REMOVE_DMI TRUE
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#define BLDOPT_REMOVE_HT_ASSIST TRUE
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#define BLDOPT_REMOVE_ATM_MODE TRUE
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//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
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//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
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#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
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//#define BLDOPT_REMOVE_C6_STATE TRUE
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#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
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#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
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/*
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* Agesa entry points used in this implementation.
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*/
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#define AGESA_ENTRY_INIT_RESET TRUE
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#define AGESA_ENTRY_INIT_RECOVERY FALSE
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#define AGESA_ENTRY_INIT_EARLY TRUE
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#define AGESA_ENTRY_INIT_POST TRUE
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#define AGESA_ENTRY_INIT_ENV TRUE
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#define AGESA_ENTRY_INIT_MID TRUE
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#define AGESA_ENTRY_INIT_LATE TRUE
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#define AGESA_ENTRY_INIT_S3SAVE TRUE
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#define AGESA_ENTRY_INIT_RESUME TRUE
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#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
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#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
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#define AGESA_ENTRY_INIT_RESET TRUE
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#define AGESA_ENTRY_INIT_RECOVERY FALSE
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#define AGESA_ENTRY_INIT_EARLY TRUE
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#define AGESA_ENTRY_INIT_POST TRUE
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#define AGESA_ENTRY_INIT_ENV TRUE
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#define AGESA_ENTRY_INIT_MID TRUE
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#define AGESA_ENTRY_INIT_LATE TRUE
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#define AGESA_ENTRY_INIT_S3SAVE TRUE
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#define AGESA_ENTRY_INIT_RESUME TRUE
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#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
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#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
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#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
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#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
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#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
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#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
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#define BLDCFG_VRM_CURRENT_LIMIT 24000
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//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
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#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
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#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
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#define BLDCFG_VRM_SLEW_RATE 5000
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//#define BLDCFG_VRM_NB_SLEW_RATE 5000
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//#define BLDCFG_VRM_ADDITIONAL_DELAY 0
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//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
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#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
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//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
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#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
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//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
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#define BLDCFG_VRM_CURRENT_LIMIT 24000
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//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
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#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
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#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
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#define BLDCFG_VRM_SLEW_RATE 5000
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//#define BLDCFG_VRM_NB_SLEW_RATE 5000
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//#define BLDCFG_VRM_ADDITIONAL_DELAY 0
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//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
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#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
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//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
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#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
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//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
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//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
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//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
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//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
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#define BLDCFG_PLAT_NUM_IO_APICS 3
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//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
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//#define BLDCFG_PLATFORM_C1E_OPDATA 0
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//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
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//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
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#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
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#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
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//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
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//#define BLDCFG_BUID_SWAP_LIST 0
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//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
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//#define BLDCFG_HTFABRIC_LIMITS_LIST 0
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//#define BLDCFG_HTCHAIN_LIMITS_LIST 0
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//#define BLDCFG_BUS_NUMBERS_LIST 0
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//#define BLDCFG_IGNORE_LINK_LIST 0
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//#define BLDCFG_LINK_SKIP_REGANG_LIST 0
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//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
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//#define BLDCFG_USE_HT_ASSIST TRUE
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//#define BLDCFG_USE_ATM_MODE TRUE
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//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
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#define BLDCFG_S3_LATE_RESTORE FALSE
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//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
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//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
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//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
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//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
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//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
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//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
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#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
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//#define BLDCFG_CFG_ABM_SUPPORT FALSE
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//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
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//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
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//#define BLDCFG_MEM_INIT_PSTATE 0
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//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
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#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
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#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
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//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
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//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
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#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
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#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
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#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
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#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
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#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
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#define BLDCFG_MEMORY_POWER_DOWN TRUE
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#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
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//#define BLDCFG_ONLINE_SPARE FALSE
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//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
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#define BLDCFG_BANK_SWIZZLE TRUE
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#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
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#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
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#define BLDCFG_DQS_TRAINING_CONTROL TRUE
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#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
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#define BLDCFG_USE_BURST_MODE FALSE
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#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
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//#define BLDCFG_ENABLE_ECC_FEATURE TRUE
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//#define BLDCFG_ECC_REDIRECTION FALSE
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//#define BLDCFG_SCRUB_DRAM_RATE 0
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//#define BLDCFG_SCRUB_L2_RATE 0
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//#define BLDCFG_SCRUB_L3_RATE 0
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//#define BLDCFG_SCRUB_IC_RATE 0
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//#define BLDCFG_SCRUB_DC_RATE 0
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//#define BLDCFG_ECC_SYNC_FLOOD 0
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//#define BLDCFG_ECC_SYMBOL_SIZE 0
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//#define BLDCFG_1GB_ALIGN FALSE
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#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
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#define BLDCFG_UMA_ALLOCATION_SIZE 0
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#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
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#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
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#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
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#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
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//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
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//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
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//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
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#define BLDCFG_PLAT_NUM_IO_APICS 3
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//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
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//#define BLDCFG_PLATFORM_C1E_OPDATA 0
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//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
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//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
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#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
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#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
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//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
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//#define BLDCFG_BUID_SWAP_LIST 0
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//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
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//#define BLDCFG_HTFABRIC_LIMITS_LIST 0
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//#define BLDCFG_HTCHAIN_LIMITS_LIST 0
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//#define BLDCFG_BUS_NUMBERS_LIST 0
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//#define BLDCFG_IGNORE_LINK_LIST 0
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//#define BLDCFG_LINK_SKIP_REGANG_LIST 0
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//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
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//#define BLDCFG_USE_HT_ASSIST TRUE
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//#define BLDCFG_USE_ATM_MODE TRUE
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//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
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#define BLDCFG_S3_LATE_RESTORE FALSE
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//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
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//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
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//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
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//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
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//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
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//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
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#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
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//#define BLDCFG_CFG_ABM_SUPPORT FALSE
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//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
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//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
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//#define BLDCFG_MEM_INIT_PSTATE 0
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//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
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#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
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#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
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//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
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//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
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#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
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#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
|
||||
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_POWER_DOWN TRUE
|
||||
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
|
||||
//#define BLDCFG_ONLINE_SPARE FALSE
|
||||
//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
|
||||
#define BLDCFG_BANK_SWIZZLE TRUE
|
||||
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
|
||||
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
|
||||
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
|
||||
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
|
||||
#define BLDCFG_USE_BURST_MODE FALSE
|
||||
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
|
||||
//#define BLDCFG_ENABLE_ECC_FEATURE TRUE
|
||||
//#define BLDCFG_ECC_REDIRECTION FALSE
|
||||
//#define BLDCFG_SCRUB_DRAM_RATE 0
|
||||
//#define BLDCFG_SCRUB_L2_RATE 0
|
||||
//#define BLDCFG_SCRUB_L3_RATE 0
|
||||
//#define BLDCFG_SCRUB_IC_RATE 0
|
||||
//#define BLDCFG_SCRUB_DC_RATE 0
|
||||
//#define BLDCFG_ECC_SYNC_FLOOD 0
|
||||
//#define BLDCFG_ECC_SYMBOL_SIZE 0
|
||||
//#define BLDCFG_1GB_ALIGN FALSE
|
||||
#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
|
||||
#define BLDCFG_UMA_ALLOCATION_SIZE 0
|
||||
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
|
||||
#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
|
||||
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
|
||||
#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
|
||||
|
||||
/*
|
||||
* Agesa configuration values selection.
|
||||
|
|
@ -259,7 +259,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
|||
#include "GnbInterface.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Define the RELEASE VERSION string
|
||||
* Define the RELEASE VERSION string
|
||||
*
|
||||
* The Release Version string should identify the next planned release.
|
||||
* When a branch is made in preparation for a release, the release manager
|
||||
|
|
@ -288,7 +288,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
|||
#define DDR1333_FREQUENCY 667 ///< DDR 1333
|
||||
#define DDR1600_FREQUENCY 800 ///< DDR 1600
|
||||
#define DDR1866_FREQUENCY 933 ///< DDR 1866
|
||||
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
|
||||
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
|
||||
|
||||
/* QUANDRANK_TYPE*/
|
||||
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
|
||||
|
|
@ -297,22 +297,22 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
|||
/* USER_MEMORY_TIMING_MODE */
|
||||
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
|
||||
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
|
||||
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
|
||||
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
|
||||
|
||||
/* POWER_DOWN_MODE */
|
||||
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
|
||||
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
|
||||
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
|
||||
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
|
||||
|
||||
// The following definitions specify the default values for various parameters in which there are
|
||||
// no clearly defined defaults to be used in the common file. The values below are based on product
|
||||
// and BKDG content, please consult the AGESA Memory team for consultation.
|
||||
#define DFLT_SCRUB_DRAM_RATE (0)
|
||||
#define DFLT_SCRUB_L2_RATE (0)
|
||||
#define DFLT_SCRUB_L3_RATE (0)
|
||||
#define DFLT_SCRUB_IC_RATE (0)
|
||||
#define DFLT_SCRUB_DC_RATE (0)
|
||||
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define DFLT_VRM_SLEW_RATE (5000)
|
||||
#define DFLT_SCRUB_DRAM_RATE (0)
|
||||
#define DFLT_SCRUB_L2_RATE (0)
|
||||
#define DFLT_SCRUB_L3_RATE (0)
|
||||
#define DFLT_SCRUB_IC_RATE (0)
|
||||
#define DFLT_SCRUB_DC_RATE (0)
|
||||
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define DFLT_VRM_SLEW_RATE (5000)
|
||||
|
||||
// Instantiate all solution relevant data.
|
||||
#include "PlatformInstall.h"
|
||||
|
|
@ -323,10 +323,10 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
|||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
|
||||
//
|
||||
|
|
@ -396,7 +396,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
|
|||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
|
||||
//DA Customer table
|
||||
// DA Customer table
|
||||
CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
|
||||
{
|
||||
// Hardcoded Memory Training Values
|
||||
|
|
|
|||
Loading…
Reference in New Issue