soc/intel/common/sa: Remove EBDA dependency

Saving cbmem_top across stages is not needed anymore so EBDA should
not be used. The guard to cbmem_top_chipset implementation was
inappropriate.

Change-Id: Ibbb3534b88de4f7b6fc39675a77461265605e56e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Arthur Heymans 2019-11-04 21:24:28 +01:00
parent c4c5d85c22
commit cf5af24a94
7 changed files with 33 additions and 30 deletions

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@ -88,7 +88,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA

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@ -3,6 +3,12 @@ config SOC_INTEL_COMMON_BLOCK_SA
help help
Intel Processor common System Agent support Intel Processor common System Agent support
config SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
bool
help
Select this if you want cbmem_top_chipset use the TOLUM returned
by the FSP HOB.
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
hex hex
default 0xe0000000 default 0xe0000000

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@ -6,3 +6,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM) += cbmem.c

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@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <fsp/util.h>
void *cbmem_top_chipset(void)
{
struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum);
return (void *)(uintptr_t)range_entry_end(&tolum);
}

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@ -19,8 +19,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <fsp/util.h>
#include <intelblocks/ebda.h>
#include <intelblocks/systemagent.h> #include <intelblocks/systemagent.h>
#include <stdlib.h> #include <stdlib.h>
@ -70,31 +68,6 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size(); *size = sa_get_tseg_size();
} }
#if CONFIG(SOC_INTEL_COMMON_BLOCK_EBDA)
void fill_memmap_ebda(struct ebda_config *cfg)
{
struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum);
cfg->cbmem_top = range_entry_end(&tolum);
}
void cbmem_top_init(void)
{
/* Initialize EBDA area */
initialize_ebda_area();
}
void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
retrieve_ebda_object(&ebda_cfg);
return (void *)(uintptr_t)ebda_cfg.cbmem_top;
}
#endif
void fill_postcar_frame(struct postcar_frame *pcf) void fill_postcar_frame(struct postcar_frame *pcf)
{ {
uintptr_t top_of_ram; uintptr_t top_of_ram;

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@ -43,7 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SA

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@ -58,7 +58,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL