soc/amd/cezanne: Add root_complex
This is a copy/paste of picasso with a few things removed. With this change we can jump into depthcharge. Allocated resources: PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6 PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b TEST=Boot majolica and see depthcharge finally loading: Starting depthcharge on MAJOLICA... new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x3004cac8 @ 00:01:07 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel
Felix Held
parent
aecca7592b
commit
cf6dc7d3a1
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@ -31,6 +31,7 @@ ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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ramstage-y += pcie_gpp.c
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ramstage-y += reset.c
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ramstage-y += root_complex.c
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ramstage-y += uart.c
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CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
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@ -0,0 +1,143 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/memmap.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <fsp/util.h>
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#include <stdint.h>
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/*
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*
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* +--------------------------------+
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* reserved_dram_end +--------------------------------+
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* | |
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* | verstage (if reqd) |
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* | (VERSTAGE_SIZE) |
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* +--------------------------------+ VERSTAGE_ADDR
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* | |
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* | FSP-M |
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* | (FSP_M_SIZE) |
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* +--------------------------------+ FSP_M_ADDR
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* | romstage |
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* | (ROMSTAGE_SIZE) |
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* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
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* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
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* | bootblock |
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* | (C_ENV_BOOTBLOCK_SIZE) |
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* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
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* | Unused hole |
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* | (86KiB) |
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* +--------------------------------+
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* | FMAP cache (FMAP_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
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* | Early Timestamp region (512B) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
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* | Preram CBMEM console |
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* | (PRERAM_CBMEM_CONSOLE_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
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* | PSP shared (vboot workbuf) |
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* | (PSP_SHAREDMEM_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE
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* | APOB (64KiB) |
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* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
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* | Early BSP stack |
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* | (EARLYRAM_BSP_STACK_SIZE) |
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* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
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* | DRAM |
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* +--------------------------------+ 0x100000
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* | Option ROM |
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* +--------------------------------+ 0xc0000
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* | Legacy VGA |
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* +--------------------------------+ 0xa0000
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* | DRAM |
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* +--------------------------------+ 0x0
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*/
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static void read_resources(struct device *dev)
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{
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uint32_t mem_usable = (uintptr_t)cbmem_top();
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unsigned int idx = 0;
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const struct hob_header *hob = fsp_get_hob_list();
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const struct hob_resource *res;
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uintptr_t early_reserved_dram_start, early_reserved_dram_end;
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const struct memmap_early_dram *e = memmap_get_early_dram_usage();
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early_reserved_dram_start = e->base;
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early_reserved_dram_end = e->base + e->size;
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/* 0x0 - 0x9ffff */
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ram_resource(dev, idx++, 0, 0xa0000 / KiB);
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/* 0xa0000 - 0xbffff: legacy VGA */
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mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
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/* 0xc0000 - 0xfffff: Option ROM */
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reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
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/* 1MiB - bottom of DRAM reserved for early coreboot usage */
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ram_resource(dev, idx++, (1 * MiB) / KiB,
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(early_reserved_dram_start - (1 * MiB)) / KiB);
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/* DRAM reserved for early coreboot usage */
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reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
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(early_reserved_dram_end - early_reserved_dram_start) / KiB);
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/*
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* top of DRAM consumed early - low top usable RAM
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* cbmem_top() accounts for low UMA and TSEG if they are used.
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*/
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ram_resource(dev, idx++, early_reserved_dram_end / KiB,
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(mem_usable - early_reserved_dram_end) / KiB);
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mmconf_resource(dev, MMIO_CONF_BASE);
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if (!hob) {
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printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n",
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__func__);
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return;
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}
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for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) {
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if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
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continue;
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res = fsp_hob_header_to_resource(hob);
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if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable)
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continue; /* 0 through low usable was set above */
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if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
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continue; /* Done separately */
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if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
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ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
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else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
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reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
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else
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printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
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res->type);
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}
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}
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static struct device_operations root_complex_operations = {
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.read_resources = read_resources,
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.set_resources = noop_set_resources,
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.enable_resources = pci_dev_enable_resources,
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};
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static const struct pci_driver family17_root_complex __pci_driver = {
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.ops = &root_complex_operations,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB,
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};
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