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skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init 

Prepare Skylake for FSP2.0 support.

We do not use FSP-T in FSP2.0 driver, hence guard the
FspTempRamInit call under a switch.

In addition to the current early PCH configuration
program few more register, so all in all we do the following,
* Program and enable ACPI Base.
* Program and enable PWRM Base.
* Program TCO Base.
* Program Interrupt configuration registers.
* Program LPC IO decode range.
* Program SMBUS Base address and enable it.
* Enable upper 128 bytes of CMOS.
And split the above programming into into smaller functions.

Also, as part of bootblock_pch_early_init we enable decoding
for HPET range. This is needed for FspMemoryInit to store and
retrieve a global data pointer.

And also move P2SB related definitions to a new header file.

TEST=Build and boot Kunimitsu

Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Rizwan Qureshi 2016-08-04 20:01:12 +05:30 committed by Martin Roth
parent 4a36c4e9fc
commit cf73c1317d
8 changed files with 177 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/soc/intel/skylake/bootblock/bootblock.c
View File

@ -14,7 +14,6 @@
*/
#include <bootblock_common.h>
#include <fsp/bootblock.h>
#include <soc/bootblock.h>
#include <soc/romstage.h>
@ -36,12 +35,14 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void)
{
/* locate and call FspTempRamInit */
bootblock_fsp_temp_ram_init();
/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
bootblock_fsp_temp_ram_init();
/*
* Perform early chipset initialization before fsp memory init
* example: pirq->irq programming, enabling smbus, pmcbase, abase,
* get platform info, i2c programming
* example: pirq->irq programming, enabling smbus, set pmcbase
* and abase, i2c programming and print platform info
*/
report_platform_info();
set_max_freq();

9
src/soc/intel/skylake/bootblock/pch.c
View File

@ -18,6 +18,7 @@
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr.h>
#include <soc/spi.h>
@ -64,6 +65,14 @@ static void enable_p2sbbar(void)
/* Enable P2SB MSE */
pci_write_config8(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/*
* Enable decoding for HPET memory address range.
* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
* the High Performance Timer memory address range
* selected by bits 1:0
*/
pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
}
void bootblock_pch_early_init(void)

7
src/soc/intel/skylake/finalize.c
View File

@ -25,6 +25,7 @@
#include <stdlib.h>
#include <soc/lpc.h>
#include <soc/me.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr.h>
#include <soc/pm.h>
@ -34,12 +35,6 @@
#include <device/pci.h>
#include <chip.h>
#define PCH_P2SB_EPMASK0 0xB0
#define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4)
#define PCH_P2SB_E0 0xE0
#define PCH_PWRM_ACPI_TMR_CTL 0xFC
static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
{
uint32_t reg32;

6
src/soc/intel/skylake/include/soc/bootblock.h
View File

@ -16,6 +16,12 @@
#ifndef _SOC_SKYLAKE_BOOTBLOCK_H_
#define _SOC_SKYLAKE_BOOTBLOCK_H_
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/bootblock.h>
#else
inline void bootblock_fsp_temp_ram_init(void) {}
#endif
/* Bootblock pre console init programing */
void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);

28
src/soc/intel/skylake/include/soc/p2sb.h Normal file
View File

@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_P2SB_H_
#define _SOC_P2SB_H_
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0xB0
#define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4)
#define PCH_P2SB_E0 0xE0
#define PCH_PWRM_ACPI_TMR_CTL 0xFC
#endif /* _SOC_P2SB_H_ */

5
src/soc/intel/skylake/include/soc/pcr.h
View File

@ -35,6 +35,11 @@
#define B_PCH_PCR_DMI_GCS_BILD (1 << 0)
#define R_PCH_PCR_DMI_LPCIOD 0x2770
#define R_PCH_PCR_DMI_LPCIOE 0x2774
#define R_PCH_PCR_DMI_ACPIBA 0x27B4
#define R_PCH_PCR_DMI_ACPIBDID 0x27B8
#define R_PCH_PCR_DMI_PMBASEA 0x27AC
#define R_PCH_PCR_DMI_PMBASEC 0x27B0
#define R_PCH_PCR_DMI_TCOBASE 0x2778
/* RTC configuration */
#define R_PCH_PCR_RTC_CONF 0x3400

12
src/soc/intel/skylake/include/soc/smbus.h
View File

@ -22,19 +22,21 @@
/* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20
#define HOSTC 0x40
#define HST_EN (1 << 0)
#define HST_EN (1 << 0)
#define SMB_RCV_SLVA 0x09
/* SMBUS TCO base address. */
#define TCOBASE 0x50
#define TCOCTL 0x54
#define SMBUS_TCO_EN (1 << 8)
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO 0x02
#define TCO2_STS_BOOT 0x04
#define TCO2_STS_SECOND_TO 0x02
#define TCO2_STS_BOOT 0x04
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
/* SMBus I/O bits. */
#define SMBHSTSTAT 0x0

141
src/soc/intel/skylake/romstage/pch.c
View File

@ -79,31 +79,6 @@ static void pch_enable_lpc(void)
pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec);
}
static void pch_device_init(void)
{
device_t dev;
u32 reg32;
u16 tcobase;
u16 tcocnt;
dev = PCH_DEV_PMC;
/* Enable ACPI and PMC mmio regs in PMC Config */
reg32 = pci_read_config32(dev, ACTL);
reg32 |= ACPI_EN | PWRM_EN;
pci_write_config32(dev, ACTL, reg32);
/* TCO timer halt */
tcobase = smbus_tco_regs();
tcocnt = inw(tcobase + TCO1_CNT);
tcocnt |= TCO_TMR_HLT;
outw(tcocnt, tcobase + TCO1_CNT);
/* Enable upper 128 bytes of CMOS */
pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, (u32)~0,
B_PCH_PCR_RTC_CONF_UCMOS_EN);
}
static void pch_interrupt_init(void)
{
u8 index = 0;
@ -120,13 +95,127 @@ static void pch_interrupt_init(void)
}
}
static void soc_config_acpibase(void)
{
uint32_t reg32;
/* Disable ABASE in PMC Device first before changing Base Address*/
reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
/* Program ACPI Base */
pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
/* Enable ACPI in PMC */
pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
/*
* Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
* to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
*/
reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);
pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32);
pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0);
}
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
/* Disable PWRMBASE in PMC Device first before changing Base address */
reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN);
/* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable PWRM in PMC */
pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);
/*
* Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0]
* to the same value programmed in PMC PCI Offset 48h bit[31:16],
* this has an implication of making sure the PWRMBASE to be
* 64KB aligned.
*
* Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
* to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
* implication of making sure the memory allocated to PWRMBASE to be 64KB
* in size.
*/
pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA,
((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
(PCH_PWRM_BASE_ADDRESS >> 16)));
pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0);
}
static void soc_config_tco(void)
{
uint32_t reg32 = 0;
uint16_t tcobase;
uint16_t tcocnt;
/* Disable TCO in SMBUS Device first before changing Base Address */
reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
reg32 &= ~SMBUS_TCO_EN;
pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
/* Program TCO Base */
pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);
/* Enable TCO in SMBUS */
pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN);
/*
* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
* to [SMBUS PCI offset 50h[15:5], 1].
*/
pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE,
(TCO_BASE_ADDDRESS | (1 << 1)));
/* Program TCO timer halt */
tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
tcobase &= ~0x1f;
tcocnt = inw(tcobase + TCO1_CNT);
tcocnt |= TCO_TMR_HLT;
outw(tcocnt, tcobase + TCO1_CNT);
}
static void soc_config_rtc(void)
{
/* Enable upper 128 bytes of CMOS */
pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0,
B_PCH_PCR_RTC_CONF_UCMOS_EN);
}
void pch_early_init(void)
{
pch_device_init();
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
* GPE0_STS, GPE0_EN registers.
*/
soc_config_acpibase();
/*
* Enabling PWRM Base for accessing
* Global Reset Cause Register.
*/
soc_config_pwrmbase();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
soc_config_tco();
/*
* Interrupt Configuration Register Programming
* PIRQx to IRQ Programming
*/
pch_interrupt_init();
/* Program generic IO Decode Range */
pch_enable_lpc();
/* Program SMBUS_BASE_ADDRESS and Enable it */
enable_smbus();
soc_config_rtc();
}