From cf9e0a08f584d47c8e6c2e3148e07d9cffe4be7f Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Tue, 6 Sep 2022 09:56:52 -0600 Subject: [PATCH] mb/google/skyrim: Add "Normal" DPTC values Add the Normal Mode DPTC values for Skyrim. These values were generated by AMD. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten Change-Id: I1e1f55b941f3e70aad33d55a90fb012eac3ba12d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67690 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- .../google/skyrim/variants/skyrim/overridetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 95e3090dc0..a9896510b1 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -245,4 +245,16 @@ chip soc/amd/mendocino end end # UART1 + # Normal + # These registers are defined in AMD DevHub document #57316. + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "sustained_power_limit_mW" = "15000" + register "thermctl_limit_degreeC" = "100" + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + end # chip soc/amd/mendocino