diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c8eaad5c25..a6eb80db36 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -4,3 +4,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) += pep.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) += sgx.c diff --git a/src/soc/intel/common/block/acpi/sgx.c b/src/soc/intel/common/block/acpi/sgx.c new file mode 100644 index 0000000000..7d9073d9ab --- /dev/null +++ b/src/soc/intel/common/block/acpi/sgx.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define SGX_RESOURCE_ENUM_CPUID_LEAF 0x12 +#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF 0x2 +#define SGX_RESOURCE_ENUM_BIT 0x1 +#define SGX_RESOURCE_MASK_LO 0xfffff000UL +#define SGX_RESOURCE_MASK_HI 0xfffffUL + +static inline uint64_t sgx_resource(uint32_t low, uint32_t high) +{ + uint64_t val; + val = (uint64_t)(high & SGX_RESOURCE_MASK_HI) << 32; + val |= low & SGX_RESOURCE_MASK_LO; + return val; +} + +void sgx_fill_ssdt(void) +{ + bool epcs = false; + struct cpuid_result cpuid_regs; + uint64_t emna = 0, elng = 0; + + if (is_sgx_supported()) { + /* + * Get EPC base and size. + * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or + * higher for enumeration of SGX resources + */ + cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF, + SGX_RESOURCE_ENUM_CPUID_SUBLEAF); + + if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { + /* EPC section enumerated */ + epcs = true; + emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); + elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); + } + + printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n", + epcs, emna, elng); + } else { + printk(BIOS_DEBUG, "SGX: not supported.\n"); + } + + acpigen_write_scope("\\_SB.EPC"); + { + acpigen_write_name_byte("EPCS", epcs); + acpigen_write_name_qword("EMNA", emna); + acpigen_write_name_qword("ELNG", elng); + } + acpigen_pop_len(); +} diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 02a9da58cf..2d3136eae6 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -105,4 +105,7 @@ void generate_acpi_power_engine(void); substate requirements */ void generate_acpi_power_engine_with_lpm(const struct soc_pmc_lpm *lpm); +/* Fill SSDT for SGX status, EPC base and length */ +void sgx_fill_ssdt(void); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 2e12bf071d..e45b34dfec 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -108,13 +108,5 @@ #define SMRR_LOCK_SUPPORTED (1<<14) #define SGX_SUPPORTED (1<<2) -/* Intel SDM: Table 36-6. - * CPUID Leaf 12H, Sub-Leaf Index 2 or Higher for enumeration of - * SGX Resources. Same Table mentions about return values of the CPUID */ -#define SGX_RESOURCE_ENUM_CPUID_LEAF (0x12) -#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF (0x2) -#define SGX_RESOURCE_ENUM_BIT (0x1) -#define SGX_RESOURCE_MASK_LO (0xfffff000UL) -#define SGX_RESOURCE_MASK_HI (0xfffffUL) #endif /* SOC_INTEL_COMMON_MSR_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index fc7282f011..3099faffba 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -5,6 +5,11 @@ #include +/* + * Check if SGX is supported + */ +int is_sgx_supported(void); + /* * Configure core PRMRR. * PRMRR needs to configured first on all cores and then @@ -17,7 +22,4 @@ void prmrr_core_configure(void); */ void sgx_configure(void *unused); -/* Fill SSDT for SGX status, EPC base and length */ -void sgx_fill_ssdt(void); - #endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index d15fc0f049..3008911491 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -13,15 +12,7 @@ #include #include -static inline uint64_t sgx_resource(uint32_t low, uint32_t high) -{ - uint64_t val; - val = (uint64_t)(high & SGX_RESOURCE_MASK_HI) << 32; - val |= low & SGX_RESOURCE_MASK_LO; - return val; -} - -static int is_sgx_supported(void) +int is_sgx_supported(void) { struct cpuid_result cpuid_regs; msr_t msr; @@ -234,41 +225,3 @@ void sgx_configure(void *unused) if (is_prmrr_approved()) activate_sgx(); } - -void sgx_fill_ssdt(void) -{ - bool epcs = false; - struct cpuid_result cpuid_regs; - uint64_t emna = 0, elng = 0; - - if (is_sgx_supported()) { - /* - * Get EPC base and size. - * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or - * Higher for enumeration of SGX Resources. Same Table mentions - * about return values of the CPUID - */ - cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF, - SGX_RESOURCE_ENUM_CPUID_SUBLEAF); - - if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { - /* EPC section enumerated */ - epcs = true; - emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); - elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); - } - - printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n", - epcs, emna, elng); - } else { - printk(BIOS_DEBUG, "SGX: not supported.\n"); - } - - acpigen_write_scope("\\_SB.EPC"); - { - acpigen_write_name_byte("EPCS", epcs); - acpigen_write_name_qword("EMNA", emna); - acpigen_write_name_qword("ELNG", elng); - } - acpigen_pop_len(); -}