src/*: Update makefiles to exclude x86 code from psp-verstage

The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor.  With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.

This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.

BUG=b:158124527
TEST=Build and boot on Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2020-06-03 19:24:11 -06:00 committed by Felix Held
parent f3343f2560
commit cfc170b213
9 changed files with 20 additions and 9 deletions

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@ -99,6 +99,13 @@ classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_mi
$(call add-special-class,all)
all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2)))
$(call add-special-class,verstage_x86)
ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
verstage_x86-handler = $(eval verstage-y += $(2))
else
verstage_x86-handler =
endif
# Add dynamic classes for rmodules
$(foreach supported_arch,$(ARCH_SUPPORTED), \
$(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))

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@ -6,7 +6,7 @@ romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
bootblock-y += boot_cpu.c
verstage-y += boot_cpu.c
verstage_x86-y += boot_cpu.c
romstage-y += boot_cpu.c
ramstage-y += boot_cpu.c
postcar-y += boot_cpu.c

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@ -2,7 +2,7 @@ ramstage-y += mtrr.c
romstage-y += earlymtrr.c
bootblock-y += earlymtrr.c
verstage-y += earlymtrr.c
verstage_x86-y += earlymtrr.c
bootblock-y += debug.c
romstage-y += debug.c
@ -10,4 +10,4 @@ postcar-y += debug.c
ramstage-y += debug.c
bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
verstage_x86-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c

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@ -1,5 +1,5 @@
bootblock-y += pgtbl.c
verstage-y += pgtbl.c
verstage_x86-y += pgtbl.c
romstage-y += pgtbl.c
postcar-y += pgtbl.c
ramstage-y += pgtbl.c

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@ -1,6 +1,6 @@
bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
verstage_x86-$(CONFIG_UDELAY_TSC) += delay_tsc.c
postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c
smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c

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@ -7,7 +7,7 @@ ramstage-$(CONFIG_SPKMODEM) += spkmodem.c
romstage-$(CONFIG_SPKMODEM) += spkmodem.c
bootblock-y += i8254.c
verstage-y += i8254.c
verstage_x86-y += i8254.c
romstage-y += i8254.c
ramstage-y += i8254.c
postcar-y += i8254.c

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@ -1,5 +1,5 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c

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@ -1,5 +1,5 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c

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@ -1,4 +1,8 @@
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c
all-y += amd_pci_mmconf.c
bootblock-y += amd_pci_mmconf.c
verstage_x86-y += amd_pci_mmconf.c
romstage-y += amd_pci_mmconf.c
postcar-y += amd_pci_mmconf.c
ramstage-y += amd_pci_mmconf.c