src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -99,6 +99,13 @@ classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_mi
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$(call add-special-class,all)
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all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2)))
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$(call add-special-class,verstage_x86)
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ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
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verstage_x86-handler = $(eval verstage-y += $(2))
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else
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verstage_x86-handler =
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endif
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# Add dynamic classes for rmodules
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$(foreach supported_arch,$(ARCH_SUPPORTED), \
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$(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
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@ -6,7 +6,7 @@ romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
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ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
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postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
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bootblock-y += boot_cpu.c
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verstage-y += boot_cpu.c
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verstage_x86-y += boot_cpu.c
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romstage-y += boot_cpu.c
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ramstage-y += boot_cpu.c
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postcar-y += boot_cpu.c
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@ -2,7 +2,7 @@ ramstage-y += mtrr.c
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romstage-y += earlymtrr.c
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bootblock-y += earlymtrr.c
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verstage-y += earlymtrr.c
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verstage_x86-y += earlymtrr.c
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bootblock-y += debug.c
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romstage-y += debug.c
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@ -10,4 +10,4 @@ postcar-y += debug.c
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ramstage-y += debug.c
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bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
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verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
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verstage_x86-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
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@ -1,5 +1,5 @@
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bootblock-y += pgtbl.c
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verstage-y += pgtbl.c
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verstage_x86-y += pgtbl.c
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romstage-y += pgtbl.c
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postcar-y += pgtbl.c
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ramstage-y += pgtbl.c
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@ -1,6 +1,6 @@
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bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
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ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
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romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
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verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
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verstage_x86-$(CONFIG_UDELAY_TSC) += delay_tsc.c
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postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c
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smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c
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@ -7,7 +7,7 @@ ramstage-$(CONFIG_SPKMODEM) += spkmodem.c
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romstage-$(CONFIG_SPKMODEM) += spkmodem.c
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bootblock-y += i8254.c
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verstage-y += i8254.c
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verstage_x86-y += i8254.c
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romstage-y += i8254.c
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ramstage-y += i8254.c
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postcar-y += i8254.c
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@ -1,5 +1,5 @@
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bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
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verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
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verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
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romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
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postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
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@ -1,5 +1,5 @@
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bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
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verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
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verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
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romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
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postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c
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@ -1,4 +1,8 @@
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c
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all-y += amd_pci_mmconf.c
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bootblock-y += amd_pci_mmconf.c
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verstage_x86-y += amd_pci_mmconf.c
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romstage-y += amd_pci_mmconf.c
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postcar-y += amd_pci_mmconf.c
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ramstage-y += amd_pci_mmconf.c
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