* split model_centaur into model_c3 and model_c7
* simplify and improve cpuid table * add speedstep support for VIA C7 based CPUs * also included as many of Uwe's suggestions as possible Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
e98edfa386
commit
cfcc9ca590
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@ -0,0 +1,30 @@
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#
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# This file is part of the coreboot project.
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#
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# (C) 2007-2008 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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||||||
|
#
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|
# You should have received a copy of the GNU General Public License
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||||||
|
# along with this program; if not, write to the Free Software
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||||||
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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dir /cpu/x86/tsc
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dir /cpu/x86/mtrr
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dir /cpu/x86/fpu
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dir /cpu/x86/mmx
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dir /cpu/x86/sse
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dir /cpu/x86/lapic
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dir /cpu/x86/cache
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dir /cpu/intel/microcode
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driver model_c3_init.o
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@ -0,0 +1,54 @@
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/*
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* This file is part of the coreboot project.
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*
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* (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||||
|
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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static void model_c3_init(device_t dev)
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{
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x86_enable_cache();
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x86_setup_mtrrs(36);
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x86_mtrr_check();
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/* Enable the local cpu apics */
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setup_lapic();
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};
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static struct device_operations cpu_dev_ops = {
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.init = model_c3_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_CENTAUR, 0x0670 }, // VIA C3 Samual 2 + Ezra
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{ X86_VENDOR_CENTAUR, 0x0680 }, // VIA C3 Ezra-T
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{ X86_VENDOR_CENTAUR, 0x0690 }, // VIA C3 Nehemiah
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{ 0, 0 },
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};
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static const struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -0,0 +1,30 @@
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#
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# This file is part of the coreboot project.
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#
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# (C) 2007-2008 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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dir /cpu/x86/tsc
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dir /cpu/x86/mtrr
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dir /cpu/x86/fpu
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dir /cpu/x86/mmx
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dir /cpu/x86/sse
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dir /cpu/x86/lapic
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dir /cpu/x86/cache
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dir /cpu/intel/microcode
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driver model_c7_init.o
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@ -0,0 +1,227 @@
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/*
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* This file is part of the coreboot project.
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*
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* (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <console/console.h>
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#include <delay.h>
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#include <stdlib.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#define MSR_IA32_PERF_STATUS 0x00000198
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#define MSR_IA32_PERF_CTL 0x00000199
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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static int c7a_speed_translation[] = {
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// LFM HFM
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0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M
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0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V
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0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V
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0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V
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0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V
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0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
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0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V
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0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV
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0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV
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0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
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0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
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};
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static int c7d_speed_translation[] = {
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// LFM HFM
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0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M
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0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V
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0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V
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0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
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0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V
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0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV
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0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV
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0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
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0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV
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0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
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0x0806, 0x1010, // 800MHz, 796mV --> 1600MHz, 956mV
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};
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static void set_c7_speed(int model) {
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int cnt, current, new, i;
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msr_t msr;
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printk_debug("Enabling improved C7 clock and voltage.\n");
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// Enable Speedstep
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msr = rdmsr(MSR_IA32_MISC_ENABLE);
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msr.lo |= (1 << 16);
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wrmsr(MSR_IA32_MISC_ENABLE, msr);
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msr = rdmsr(MSR_IA32_PERF_STATUS);
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printk_info("Voltage: %dmV (min %dmV; max %dmV)\n",
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((int)(msr.lo & 0xff) * 16 + 700),
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((int)((msr.hi >> 16) & 0xff) * 16 + 700),
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((int)(msr.hi & 0xff) * 16 + 700));
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printk_info("CPU multiplier: %dx (min %dx; max %dx)\n",
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(int)((msr.lo >> 8) & 0xff),
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(int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
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printk_debug(" msr.lo = %x\n", msr.lo);
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/* Wait while CPU is busy */
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cnt = 0;
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while (msr.lo & ((1 << 16) | (1 << 17))) {
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udelay(16);
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msr = rdmsr(MSR_IA32_PERF_STATUS);
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cnt++;
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if (cnt > 128) {
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printk_warning("Could not update multiplier and voltage.\n");
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return;
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}
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}
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current = msr.lo & 0xffff;
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// Start out with no change.
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new = current;
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switch (model) {
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case 10: // model A
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for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) {
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if ((c7a_speed_translation[i] == current) &&
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((c7a_speed_translation[i + 1] & 0xff00) ==
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(msr.hi & 0xff00))) {
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new = c7a_speed_translation[i + 1];
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}
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}
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break;
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case 13: // model D
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for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) {
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if ((c7d_speed_translation[i] == current) &&
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((c7d_speed_translation[i + 1] & 0xff00) ==
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(msr.hi & 0xff00))) {
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new = c7d_speed_translation[i + 1];
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}
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|
}
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break;
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default:
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print_info("CPU type not known, multiplier unchanged.\n");
|
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|
}
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|
|
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msr.lo = new;
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msr.hi = 0;
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printk_debug(" new msr.lo = %x\n", msr.lo);
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|
|
||||||
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wrmsr(MSR_IA32_PERF_CTL, msr);
|
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|
|
||||||
|
/* Wait until the power transition ends */
|
||||||
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cnt = 0;
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||||||
|
do {
|
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|
udelay(16);
|
||||||
|
msr = rdmsr(MSR_IA32_PERF_STATUS);
|
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|
cnt++;
|
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|
if (cnt > 128) {
|
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|
printk_warning("Error while updating multiplier and voltage\n");
|
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|
break;
|
||||||
|
}
|
||||||
|
} while (msr.lo & ((1 << 16) | (1 << 17)));
|
||||||
|
|
||||||
|
printk_info("Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
|
||||||
|
printk_info("Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void model_c7_init(device_t dev)
|
||||||
|
{
|
||||||
|
u8 brand;
|
||||||
|
struct cpuinfo_x86 c;
|
||||||
|
msr_t msr;
|
||||||
|
|
||||||
|
get_fms(&c, dev->device);
|
||||||
|
|
||||||
|
printk_info("Detected VIA ");
|
||||||
|
|
||||||
|
switch (c.x86_model) {
|
||||||
|
case 10:
|
||||||
|
msr = rdmsr(0x1153);
|
||||||
|
brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
|
||||||
|
printk_info("Model A ");
|
||||||
|
break;
|
||||||
|
case 13:
|
||||||
|
msr = rdmsr(0x1154);
|
||||||
|
brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
|
||||||
|
printk_info("Model D ");
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printk_info("Model Unknown ");
|
||||||
|
brand = 0xff;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (brand) {
|
||||||
|
case 0:
|
||||||
|
printk_info("C7-M\n");
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
printk_info("C7\n");
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
printk_info("Eden\n");
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
printk_info("C7-D\n");
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printk_info("%02x (please report)\n", brand);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Gear up */
|
||||||
|
set_c7_speed(c.x86_model);
|
||||||
|
|
||||||
|
/* Turn on cache */
|
||||||
|
x86_enable_cache();
|
||||||
|
|
||||||
|
/* Set up Memory Type Range Registers */
|
||||||
|
x86_setup_mtrrs(36);
|
||||||
|
x86_mtrr_check();
|
||||||
|
|
||||||
|
/* Enable the local cpu apics */
|
||||||
|
setup_lapic();
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct device_operations cpu_dev_ops = {
|
||||||
|
.init = model_c7_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Look in arch/i386/lib/cpu.c:cpu_initialize. If there is no CPU with an exact
|
||||||
|
* ID, the cpu mask (stepping) is masked out and the check is repeated. This
|
||||||
|
* allows us to keep the table significantly smaller.
|
||||||
|
*/
|
||||||
|
|
||||||
|
static struct cpu_device_id cpu_table[] = {
|
||||||
|
{X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther
|
||||||
|
{X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M
|
||||||
|
{0, 0},
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct cpu_driver driver __cpu_driver = {
|
||||||
|
.ops = &cpu_dev_ops,
|
||||||
|
.id_table = cpu_table,
|
||||||
|
};
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
dir /cpu/x86/tsc
|
|
||||||
dir /cpu/x86/mtrr
|
|
||||||
dir /cpu/x86/fpu
|
|
||||||
dir /cpu/x86/mmx
|
|
||||||
dir /cpu/x86/sse
|
|
||||||
dir /cpu/x86/lapic
|
|
||||||
dir /cpu/x86/cache
|
|
||||||
driver model_centaur_init.o
|
|
||||||
|
|
@ -1,66 +0,0 @@
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <cpu/cpu.h>
|
|
||||||
#include <cpu/x86/mtrr.h>
|
|
||||||
#include <cpu/x86/msr.h>
|
|
||||||
#include <cpu/x86/lapic.h>
|
|
||||||
#include <cpu/x86/cache.h>
|
|
||||||
#include <cpu/x86/mtrr.h>
|
|
||||||
|
|
||||||
static void model_centaur_init(device_t dev)
|
|
||||||
{
|
|
||||||
/* Turn on caching if we haven't already */
|
|
||||||
x86_enable_cache();
|
|
||||||
x86_setup_mtrrs(36);
|
|
||||||
x86_mtrr_check();
|
|
||||||
|
|
||||||
/* Enable the local cpu apics */
|
|
||||||
setup_lapic();
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct device_operations cpu_dev_ops = {
|
|
||||||
.init = model_centaur_init,
|
|
||||||
};
|
|
||||||
|
|
||||||
#warning "FIXME - need correct cpu id here for VIA C3"
|
|
||||||
static struct cpu_device_id cpu_table[] = {
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0670 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0671 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0672 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0673 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0674 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0675 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0676 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0677 }, // VIA C3 Samual 2
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0678 }, // VIA C3 Ezra
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0680 }, // VIA C3 Ezra-T
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0691 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0692 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0693 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0694 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0695 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0696 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0697 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0698 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x0699 }, // VIA C3 Nehemiah
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x069A }, // VIA C3 Nehemiah
|
|
||||||
/* Some of these may not actually exist */
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06A0 }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06A8 }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06A9 }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06AA }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06AB }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06AC }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06AD }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06AE }, // VIA C7 Esther
|
|
||||||
{ X86_VENDOR_CENTAUR, 0x06AF }, // VIA C7 Esther
|
|
||||||
{ 0, 0 },
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct cpu_driver driver __cpu_driver = {
|
|
||||||
.ops = &cpu_dev_ops,
|
|
||||||
.id_table = cpu_table,
|
|
||||||
};
|
|
||||||
|
|
@ -134,7 +134,7 @@ config chip.h
|
||||||
chip northbridge/via/vt8623
|
chip northbridge/via/vt8623
|
||||||
|
|
||||||
device apic_cluster 0 on
|
device apic_cluster 0 on
|
||||||
chip cpu/via/model_centaur
|
chip cpu/via/model_c3
|
||||||
device apic 0 on end
|
device apic 0 on end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -184,7 +184,7 @@ chip northbridge/via/vt8601
|
||||||
end
|
end
|
||||||
|
|
||||||
device apic_cluster 0 on
|
device apic_cluster 0 on
|
||||||
chip cpu/via/model_centaur
|
chip cpu/via/model_c3
|
||||||
device apic 0 on end
|
device apic 0 on end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue