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mb/**/dsdt.asl: Remove outdated sleepstates.asl comment 

Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

This follows commit 408d1dac9e.

Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-03-01 02:12:58 +01:00 committed by Patrick Georgi
parent 59e7a43f9a
commit cfe1016883
4 changed files with 0 additions and 4 deletions
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1
src/mainboard/google/dedede/dsdt.asl
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@ -38,7 +38,6 @@ DefinitionBlock(
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/google/volteer/dsdt.asl
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@ -47,6 +47,5 @@ DefinitionBlock(
#include <ec/google/chromeec/acpi/ec.asl> #include <ec/google/chromeec/acpi/ec.asl>
} }
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/jasperlake_rvp/dsdt.asl
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@ -58,7 +58,6 @@ DefinitionBlock(
} }
#endif #endif
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */ /* Mainboard specific */

1
src/mainboard/intel/tglrvp/dsdt.asl
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@ -58,7 +58,6 @@ DefinitionBlock(
} }
#endif #endif
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */ /* Mainboard specific */