southbridge/intel/lynxpoint: refactor rtc failure checking

In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.

BUG=b:63054105

Change-Id: I368c31b9935c0fa9e8a1be416435dd76f44ec1ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/southbridge/intel/lynxpoint/Makefile.inc

@@ -49,7 +49,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c
 
 romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
-romstage-y += reset.c early_spi.c rcba.c
+romstage-y += reset.c early_spi.c rcba.c pmutil.c
 
 ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
 romstage-y += lp_gpio.c

src/southbridge/intel/lynxpoint/lpc.c

@@ -284,18 +284,14 @@ static void pch_power_options(device_t dev)
 
 static void pch_rtc_init(struct device *dev)
 {
-	u8 reg8;
+	int rtc_failed = rtc_failure();
-	int rtc_failed;
 
-	reg8 = pci_read_config8(dev, GEN_PMCON_3);
-	rtc_failed = reg8 & RTC_BATTERY_DEAD;
 	if (rtc_failed) {
-		reg8 &= ~RTC_BATTERY_DEAD;
+		if (IS_ENABLED(CONFIG_ELOG))
-		pci_write_config8(dev, GEN_PMCON_3, reg8);
+			elog_add_event(ELOG_TYPE_RTC_RESET);
-#if IS_ENABLED(CONFIG_ELOG)
+		pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0);
-		elog_add_event(ELOG_TYPE_RTC_RESET);
-#endif
 	}
+
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
 	cmos_init(rtc_failed);

src/southbridge/intel/lynxpoint/pch.h

@@ -172,6 +172,9 @@ void disable_all_gpe(void);
 void enable_gpe(u32 mask);
 void disable_gpe(u32 mask);
 
+/* Return non-zero when RTC failure happened. */
+int rtc_failure(void);
+
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
 #include <arch/acpi.h>

src/southbridge/intel/lynxpoint/pmutil.c

@@ -553,3 +553,13 @@ void disable_gpe(u32 mask)
 	gpe0_en &= ~mask;
 	outl(gpe0_en, get_pmbase() + gpe0_reg);
 }
+
+int rtc_failure(void)
+{
+#if defined(__SIMPLE_DEVICE__)
+	device_t dev = PCI_DEV(0, 31, 0);
+#else
+	device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+#endif
+	return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
+}