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mb/google/brya/var/vell: add WWAN power sequence setting for vell 

Add WWAN power sequence setting to meet spec

BUG=b:220084872
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Robert Chen 2022-02-11 15:45:26 +08:00 committed by Felix Held
parent 74ec3efcad
commit cfe9253773
2 changed files with 16 additions and 3 deletions
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17
src/mainboard/google/brya/variants/vell/gpio.c
View File

@ -39,11 +39,17 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG),
/* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */ /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */
PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */ /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */
PAD_CFG_GPI(GPP_E22, NONE, DEEP), PAD_CFG_GPI(GPP_E22, NONE, DEEP),
/* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */ /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
/*
* E0 : SATAXPCIE0 ==> WWAN_PERST_L
* Drive high here, so that PERST_L is sequenced after RST_L
*/
PAD_CFG_GPO(GPP_E0, 1, DEEP),
/* F19 : NC */ /* F19 : NC */
PAD_NC(GPP_F19, NONE), PAD_NC(GPP_F19, NONE),
@ -94,6 +100,8 @@ static const struct pad_config override_gpio_table[] = {
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> SSD_PERST_L */ /* B4 : PROC_GP3 ==> SSD_PERST_L */
@ -117,7 +125,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_D3, 1, DEEP), PAD_CFG_GPO(GPP_D3, 1, DEEP),
/* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */ /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
PAD_CFG_GPO(GPP_E0, 0, DEEP),
/* E3 : PROC_GP0 ==> MEM_STRAP_0 */ /* E3 : PROC_GP0 ==> MEM_STRAP_0 */
PAD_CFG_GPI(GPP_E3, NONE, DEEP), PAD_CFG_GPI(GPP_E3, NONE, DEEP),
/* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */ /* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */
@ -131,6 +140,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_E16, 0, DEEP), PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP), PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_F21, 0, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
@ -162,6 +173,8 @@ static const struct pad_config early_gpio_table[] = {
static const struct pad_config romstage_gpio_table[] = { static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */ /* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP), PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
PAD_CFG_GPO(GPP_F21, 1, DEEP),
}; };
const struct pad_config *variant_romstage_gpio_table(size_t *num) const struct pad_config *variant_romstage_gpio_table(size_t *num)

2
src/mainboard/google/brya/variants/vell/overridetree.cb
View File

@ -196,7 +196,7 @@ chip soc/intel/alderlake
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
register "add_acpi_dma_property" = "true" register "add_acpi_dma_property" = "true"
use rp6_rtd3 as rtd3dev use rp6_rtd3 as rtd3dev
device generic 0 on end device generic 0 alias rp6_wwan on end
end end
end end
device ref pcie_rp8 off end device ref pcie_rp8 off end