mb/google/brya/var/vell: add WWAN power sequence setting for vell
Add WWAN power sequence setting to meet spec BUG=b:220084872 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -39,11 +39,17 @@ static const struct pad_config override_gpio_table[] = {
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PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG),
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/* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */
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PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG),
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/* E16 : RSVD_TP ==> WWAN_RST_L */
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PAD_CFG_GPO(GPP_E16, 1, DEEP),
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/* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */
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PAD_CFG_GPI(GPP_E22, NONE, DEEP),
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/* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */
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PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
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/*
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* E0 : SATAXPCIE0 ==> WWAN_PERST_L
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* Drive high here, so that PERST_L is sequenced after RST_L
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*/
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PAD_CFG_GPO(GPP_E0, 1, DEEP),
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/* F19 : NC */
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PAD_NC(GPP_F19, NONE),
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@ -94,6 +100,8 @@ static const struct pad_config override_gpio_table[] = {
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
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PAD_CFG_GPO(GPP_A12, 1, DEEP),
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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@ -117,7 +125,8 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_D3, 1, DEEP),
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/* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */
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PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
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/* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
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PAD_CFG_GPO(GPP_E0, 0, DEEP),
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/* E3 : PROC_GP0 ==> MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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/* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */
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@ -131,6 +140,8 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_E16, 0, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
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PAD_CFG_GPO(GPP_F21, 0, DEEP),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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@ -162,6 +173,8 @@ static const struct pad_config early_gpio_table[] = {
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static const struct pad_config romstage_gpio_table[] = {
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
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PAD_CFG_GPO(GPP_F21, 1, DEEP),
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};
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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@ -196,7 +196,7 @@ chip soc/intel/alderlake
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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device generic 0 on end
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device generic 0 alias rp6_wwan on end
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end
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end
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device ref pcie_rp8 off end
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