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nb/intel/i945: Refactor `get_pcie_bar` 

Turn it into `decode_pcie_bar`, taken from gm45.

Change-Id: I81a398535f18ced10b5521bddcf21f3568e1d854
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-08-03 16:11:53 +02:00
parent 1850396dc4
commit cff4d1649f
1 changed files with 20 additions and 19 deletions
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39
src/northbridge/intel/i945/northbridge.c
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> #include <cbmem.h>
#include <commonlib/helpers.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <stdint.h> #include <stdint.h>
@ -11,32 +12,33 @@
#include <cpu/intel/smm_reloc.h> #include <cpu/intel/smm_reloc.h>
#include "i945.h" #include "i945.h"
static int get_pcie_bar(u32 *base) static int decode_pcie_bar(u32 *const base, u32 *const len)
{ {
struct device *dev;
u32 pciexbar_reg;
*base = 0; *base = 0;
*len = 0;
dev = pcidev_on_root(0, 0); struct device *dev = pcidev_on_root(0, 0);
if (!dev) if (!dev)
return 0; return 0;
pciexbar_reg = pci_read_config32(dev, PCIEXBAR); const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0))) if (!(pciexbar_reg & (1 << 0)))
return 0; return 0;
switch ((pciexbar_reg >> 1) & 3) { switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB case 0: /* 256MB */
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); *base = pciexbar_reg & (0x0f << 28);
return 256; *len = 256 * MiB;
case 1: // 128M return 1;
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); case 1: /* 128M */
return 128; *base = pciexbar_reg & (0x1f << 27);
case 2: // 64M *len = 128 * MiB;
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); return 1;
return 64; case 2: /* 64M */
*base = pciexbar_reg & (0x3f << 26);
*len = 64 * MiB;
return 1;
} }
return 0; return 0;
@ -162,13 +164,12 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(struct device *dev) static void mc_read_resources(struct device *dev)
{ {
u32 pcie_config_base; u32 pcie_config_base, pcie_config_len;
int buses;
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
buses = get_pcie_bar(&pcie_config_base); if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) {
if (buses) { const int buses = pcie_config_len / MiB;
struct resource *resource = new_resource(dev, PCIEXBAR); struct resource *resource = new_resource(dev, PCIEXBAR);
mmconf_resource_init(resource, pcie_config_base, buses); mmconf_resource_init(resource, pcie_config_base, buses);
} }