soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig

This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT
from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file
and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc.

Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2019-01-30 11:35:18 +05:30
parent 45ad4f041b
commit cff6a1df3b
5 changed files with 1 additions and 8 deletions

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@ -13,7 +13,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_COFFEELAKE select SOC_INTEL_COFFEELAKE
select SYSTEM_TYPE_LAPTOP select SYSTEM_TYPE_LAPTOP

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@ -15,7 +15,6 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
select SOC_INTEL_COFFEELAKE select SOC_INTEL_COFFEELAKE
select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_HDA_VERB

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@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_I2C_HID select DRIVERS_I2C_HID
select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GENERIC
select SOC_INTEL_COFFEELAKE select SOC_INTEL_COFFEELAKE
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8
select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP
select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP

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@ -170,10 +170,6 @@ config CPU_BCLK_MHZ
int int
default 100 default 100
config SOC_INTEL_CANNONLAKE_MEMCFG_INIT
bool
default n
config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int int
default 120 default 120

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@ -21,7 +21,7 @@ bootblock-y += lpc.c
bootblock-y += p2sb.c bootblock-y += p2sb.c
bootblock-y += uart.c bootblock-y += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c romstage-y += cnl_memcfg_init.c
romstage-y += gspi.c romstage-y += gspi.c
romstage-y += i2c.c romstage-y += i2c.c
romstage-y += lpc.c romstage-y += lpc.c