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sb/intel/lynxpoint/sata: Simplify RMW operations 

Introduce the `sir_unset_and_set_mask` helper and update the one PCI
read-modify-write operation that is somehow not reproducible.

Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons 2020-10-30 12:56:02 +01:00
parent 2f572dd964
commit d00af4fbac
1 changed files with 13 additions and 18 deletions
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31
src/southbridge/intel/lynxpoint/sata.c
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@ -25,10 +25,17 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
pci_write_config32(dev, SATA_SIRD, value); pci_write_config32(dev, SATA_SIRD, value);
} }
static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set)
{
pci_write_config32(dev, SATA_SIRI, idx);
const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset;
pci_write_config32(dev, SATA_SIRD, value | set);
}
static void sata_init(struct device *dev) static void sata_init(struct device *dev)
{ {
u32 reg32; u32 reg32;
u16 reg16;
u32 *abar; u32 *abar;
@ -69,10 +76,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, IDE_CONFIG, reg32); pci_write_config32(dev, IDE_CONFIG, reg32);
/* for AHCI, Port Enable is managed in memory mapped space */ /* for AHCI, Port Enable is managed in memory mapped space */
reg16 = pci_read_config16(dev, 0x92); pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map);
reg16 &= ~0x3f;
reg16 |= 0x8000 | config->sata_port_map;
pci_write_config16(dev, 0x92, reg16);
udelay(2); udelay(2);
/* Setup register 98h */ /* Setup register 98h */
@ -173,25 +177,16 @@ static void sata_init(struct device *dev)
sir_write(dev, 0x64, 0x883c9001); sir_write(dev, 0x64, 0x883c9001);
/* Step 2: SIR 68h[15:0] = 880Ah */ /* Step 2: SIR 68h[15:0] = 880Ah */
reg32 = sir_read(dev, 0x68); sir_unset_and_set_mask(dev, 0x68, 0xffff, 0x880a);
reg32 &= 0xffff0000;
reg32 |= 0x880a;
sir_write(dev, 0x68, reg32);
/* Step 3: SIR 60h[3] = 1 */ /* Step 3: SIR 60h[3] = 1 */
reg32 = sir_read(dev, 0x60); sir_unset_and_set_mask(dev, 0x60, 0, 1 << 3);
reg32 |= (1 << 3);
sir_write(dev, 0x60, reg32);
/* Step 4: SIR 60h[0] = 1 */ /* Step 4: SIR 60h[0] = 1 */
reg32 = sir_read(dev, 0x60); sir_unset_and_set_mask(dev, 0x60, 0, 1 << 0);
reg32 |= (1 << 0);
sir_write(dev, 0x60, reg32);
/* Step 5: SIR 60h[1] = 1 */ /* Step 5: SIR 60h[1] = 1 */
reg32 = sir_read(dev, 0x60); sir_unset_and_set_mask(dev, 0x60, 0, 1 << 1);
reg32 |= (1 << 1);
sir_write(dev, 0x60, reg32);
/* Clock Gating */ /* Clock Gating */
sir_write(dev, 0x70, 0x3f00bf1f); sir_write(dev, 0x70, 0x3f00bf1f);