mb/supermicro: Add X9SAE and X9SAE-V
Mainboard information can be found in the included documentation. Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Bill XIE
Felix Held
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d00febc99b
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# Supermicro X9SAE and X9SAE-V
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This page describes how to run coreboot on the Supermicro [X9SAE] and [X9SAE-V]
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## Flashing coreboot
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```eval_rst
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+---------------------+----------------+
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| Type | Value |
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+=====================+================+
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| Socketed flash | occasionally |
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+---------------------+----------------+
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| Model | W25Q128FVSG |
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+---------------------+----------------+
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| Size | 16 MiB |
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+---------------------+----------------+
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| Package | SOIC-8 |
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+---------------------+----------------+
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| Write protection | no |
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+---------------------+----------------+
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| Dual BIOS feature | no |
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+---------------------+----------------+
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| Internal flashing | yes |
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+---------------------+----------------+
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```
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The flash IC is located between the PCH and the front panel connector,
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(circled) sometimes it is socketed.
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### How to flash
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Unlike ordinary desktop boards, the BIOS version 2.00 of X9SAE-V does not
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apply any write protection, so the main SPI flash can be accessed using
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[flashrom], and the whole flash is writable.
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Note: If you are going to modify the ME region via internal programming, you had
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better disable ME functionalities as much as possible in the vendor firmware
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first, otherwise ME may write something back and break the firmware you write.
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The following command may be used to flash coreboot. (To do so, linux kernel
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could be started with `iomem=relaxed` or unload the `lpc_ich` kernel module)
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Now you can [flash internally](/flash_tutorial/int_flashrom.md). It is
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recommended to flash only the `bios` region (use `--ifd -i bios -N` flashrom
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arguments), in order to minimize the chances of messing something up in the
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beginning.
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The flash chip is a SOIC-8 SPI flash, and may be socketed, so it's also easy
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to do in-system programming, or remove and flash externally if it is socketed.
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## Difference between X9SAE and X9SAE-V
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On X9SAE PCI-E slot 4 is absent. Lane 9~16 of PCI-E slot 6 on X9SAE are wired
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to slot 4 on X9SAE-V. Unlike ASUS P8C WS, there is no dynamic switch on X9SAE-V,
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so on X9SAE-V slot 6 can work as x8 at most.
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On X9SAE-V device pci 01.1 appears even if not defined in devicetree.cb, so it
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seems that it shall not appear on X9SAE even if it is defined.
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## Working (on my X9SAE-V)
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- Intel Xeon E3-1225 V2 with 4 M391B1G73BH0-YK0 UDIMMs, ECC confirmed active
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- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.46
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- Use PS/2 keyboard and mouse simutaneously with a PS/2 Y-cable
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- Both Onboard NIC
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- S3 Suspend to RAM
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- USB2 on rear and front panel connectors
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- USB3
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- Integrated SATA
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- CPU Temp sensors (tested PSensor on GNU/Linux)
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- LPC TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
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- Native raminit
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- Integrated graphics with libgfxinit
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- Nvidia Quadro 600 in all PCIe-16x slots
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- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot
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- Debug output from serial port
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## Untested
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- EHCI debugging
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- S/PDIF audio
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- PS/2 mouse
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6776F |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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## Extra resources
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- [Flash chip datasheet][W25Q128FVSG]
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[X9SAE]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm
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[X9SAE-V]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm
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[W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf
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[flashrom]: https://flashrom.org/Flashrom
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_SUPERMICRO_X9SAE
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_INT15
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_USES_IFD_GBE_REGION
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_NUVOTON_NCT6776
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select USE_NATIVE_RAMINIT
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config MAINBOARD_DIR
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string
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default "supermicro/x9sae"
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config MAINBOARD_PART_NUMBER
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string
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default "X9SAE"
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endif
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config BOARD_SUPERMICRO_X9SAE
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bool "X9SAE"
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += early_init.c
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bootblock-y += gpio.c
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romstage-y += early_init.c
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romstage-y += gpio.c
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ramstage-y += hda_verb.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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/* SPDX-License-Identifier: GPL-2.0-only */
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// Intel PCI to PCI bridge 0:1e.0
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Device (PCIB)
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{
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Name (_ADR, 0x001E0000) // _ADR: Address
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Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
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Method (_PRT) // _PRT: PCI Interrupt Routing Table
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0001ffff, 0, 0, 0x16 },
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Package() { 0x0001ffff, 1, 0, 0x15 },
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Package() { 0x0001ffff, 2, 0, 0x14 },
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Package() { 0x0001ffff, 3, 0, 0x13 },
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Package() { 0x0002ffff, 0, 0, 0x12 },
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Package() { 0x0002ffff, 1, 0, 0x13 },
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Package() { 0x0002ffff, 2, 0, 0x11 },
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Package() { 0x0002ffff, 3, 0, 0x10 },
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Package() { 0x0003ffff, 0, 0, 0x13 },
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Package() { 0x0003ffff, 1, 0, 0x12 },
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Package() { 0x0003ffff, 2, 0, 0x15 },
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Package() { 0x0003ffff, 3, 0, 0x16 },
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Package() { 0x0000ffff, 0, 0, 0x10 },
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Package() { 0x0000ffff, 1, 0, 0x11 },
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Package() { 0x0000ffff, 2, 0, 0x12 },
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Package() { 0x0000ffff, 3, 0, 0x13 },
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})
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}
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Return (Package() {
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0 },
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Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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})
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}
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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Method(_WAK, 1)
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{
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Return(Package() {0, 0})
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}
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Method(_PTS, 1)
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{
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}
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Category: desktop
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Board URL: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: Occasionally
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Flashrom support: y
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Release year: 2012
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boot_option=Fallback
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debug_level=Debug
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nmi=Disable
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power_on_after_fail=Disable
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sata_mode=AHCI
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gfx_uma_size=64M
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 3 debug_level
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 4 power_on_after_fail
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411 2 e 5 sata_mode
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# coreboot config options: northbridge
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416 5 e 6 gfx_uma_size
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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# Generic on/off enum
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1 0 Disable
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1 1 Enable
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# boot_option
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2 0 Fallback
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2 1 Normal
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# debug_level
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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# power_on_after_fail
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4 0 Disable
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4 1 Enable
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4 2 Keep
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# sata_mode
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5 0 AHCI
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5 1 Compatible
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5 2 Legacy
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# gfx_uma_size (Intel IGP Video RAM size)
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6 0 32M
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6 1 64M
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6 2 96M
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6 3 128M
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6 4 160M
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6 5 192M
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6 6 224M
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6 7 256M
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6 8 288M
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6 9 320M
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6 10 352M
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6 11 384M
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6 12 416M
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6 13 448M
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6 14 480M
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6 15 512M
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6 16 1024M
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# -----------------------------------------------------------------
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checksums
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checksum 392 423 984
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Binary file not shown.
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## SPDX-License-Identifier: GPL-2.0-only
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chip northbridge/intel/sandybridge
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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register "gpu_dp_b_hotplug" = "4"
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register "gpu_dp_c_hotplug" = "4"
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register "gpu_dp_d_hotplug" = "4"
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register "gpu_panel_power_cycle_delay" = "4"
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device cpu_cluster 0 on
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chip cpu/intel/model_206ax
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register "acpi_c1" = "1"
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register "acpi_c2" = "3"
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register "acpi_c3" = "5"
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device lapic 0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0 on
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subsystemid 0x15d9 0x0644 inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # CPU1 SLOT6 (x8 or x16)
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device pci 01.1 on end # CPU1 SLOT4 (electrical x8 in x16 if present)
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device pci 02.0 on end # iGPU
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device pci 06.0 on end # CPU1 SLOT7 (electrical x4 in x8)
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chip southbridge/intel/bd82x6x
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register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff)
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3f"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # xHCI
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device pci 16.0 on end # MEI #1
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device pci 16.1 off end # MEI #2
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device pci 16.2 off end # ME IDE-R
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device pci 16.3 off end # ME KT
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device pci 19.0 on end # Intel GbE LAN1
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device pci 1a.0 on end # EHCI #2
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device pci 1b.0 on end # HD Audio
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device pci 1c.0 on end # RP #1 PCH SLOT2
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device pci 1c.1 off end # RP #2
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device pci 1c.2 off end # RP #3
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device pci 1c.3 off end # RP #4
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device pci 1c.4 on end # RP #5 PCH SLOT3
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device pci 1c.5 off end # RP #6
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device pci 1c.6 on end # RP #7 PCH SLOT5
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device pci 1c.7 on # RP #8
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device pci 00.0 on end # 574 GbE LAN2
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end
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device pci 1d.0 on end # EHCI #1
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/nuvoton/nct6776
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 off end # Parallel port
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2, IR
|
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x060
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io 0x62 = 0x064
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
|
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device pnp 2e.7 off end # GPIO6
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device pnp 2e.107 off end # GPIO7
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device pnp 2e.207 off end # GPIO8
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device pnp 2e.307 off end # GPIO9
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device pnp 2e.8 off end # WDT
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device pnp 2e.108 on end # GPIO0
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device pnp 2e.208 off end # GPIOA
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device pnp 2e.308 on # GPIOBASE
|
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io 0x60 = 0xa00
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end
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device pnp 2e.109 off end # GPIO1
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device pnp 2e.209 on end # GPIO2
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device pnp 2e.309 off end # GPIO3
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device pnp 2e.409 off end # GPIO4
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device pnp 2e.509 off end # GPIO5
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device pnp 2e.609 off end # GPIO6
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device pnp 2e.709 off end # GPIO7
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device pnp 2e.a on # ACPI
|
||||
irq 0xe0 = 0
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irq 0xe4 = 0x60
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irq 0xe6 = 0x4c
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irq 0xe7 = 0x10
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irq 0xf2 = 0x5d
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end
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device pnp 2e.b on # HWM, front panel LED
|
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io 0x60 = 0xa30
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io 0x62 = 0xa80
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irq 0x70 = 0
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||||
irq 0xf8 = 0x43
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end
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device pnp 2e.d off end # VID
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device pnp 2e.e off end # CIR WAKE-UP
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device pnp 2e.f off end # GPIO
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||||
device pnp 2e.14 off end # SVID
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||||
device pnp 2e.16 off end # Deep sleep
|
||||
device pnp 2e.17 off end # GPIOA
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||||
end
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chip drivers/pc80/tpm
|
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device pnp c31.0 on end # TPM
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||||
end
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||||
end
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device pci 1f.2 on end # SATA (AHCI)
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||||
device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA (Legacy)
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device pci 1f.6 off end # Thermal
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||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20141018 /* OEM revision */
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include "acpi/platform.asl"
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
#include <southbridge/intel/common/acpi/platform.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
#include "acpi/pci.asl"
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <device/pnp_ops.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
#include <superio/nuvoton/nct6776/nct6776.h>
|
||||
|
||||
#define GLOBAL_DEV PNP_DEV(0x2e, 0)
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
|
||||
#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 0, 0 },
|
||||
{ 1, 0, 0 },
|
||||
{ 1, 0, 1 },
|
||||
{ 1, 0, 1 },
|
||||
{ 1, 0, 2 },
|
||||
{ 1, 0, 2 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 0, 4 },
|
||||
{ 1, 0, 4 },
|
||||
{ 1, 0, 6 },
|
||||
{ 1, 0, 5 },
|
||||
{ 1, 0, 5 },
|
||||
{ 1, 0, 6 },
|
||||
};
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
|
||||
|
||||
/* Select SIO pin states */
|
||||
pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8);
|
||||
pnp_write_config(GLOBAL_DEV, 0x1b, 0x6d);
|
||||
pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
|
||||
pnp_write_config(GLOBAL_DEV, 0x24, 0x24);
|
||||
pnp_write_config(GLOBAL_DEV, 0x2a, 0x00);
|
||||
pnp_write_config(GLOBAL_DEV, 0x2b, 0x02);
|
||||
pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
|
||||
|
||||
/* Power RAM in S3 */
|
||||
pnp_set_logical_device(ACPI_DEV);
|
||||
pnp_write_config(ACPI_DEV, 0xe4, 0x10);
|
||||
|
||||
pnp_set_logical_device(SERIAL_DEV);
|
||||
|
||||
nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
|
||||
|
||||
/* Enable UART */
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[0], 0x50, id_only);
|
||||
read_spd(&spd[1], 0x51, id_only);
|
||||
read_spd(&spd[2], 0x52, id_only);
|
||||
read_spd(&spd[3], 0x53, id_only);
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1,
|
||||
HDMI2,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_NATIVE,
|
||||
.gpio3 = GPIO_MODE_NATIVE,
|
||||
.gpio4 = GPIO_MODE_NATIVE,
|
||||
.gpio5 = GPIO_MODE_NATIVE,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_NATIVE,
|
||||
.gpio12 = GPIO_MODE_NATIVE,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_NATIVE,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_OUTPUT,
|
||||
.gpio15 = GPIO_DIR_INPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio21 = GPIO_DIR_OUTPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio14 = GPIO_LEVEL_LOW,
|
||||
.gpio21 = GPIO_LEVEL_HIGH,
|
||||
.gpio24 = GPIO_LEVEL_HIGH,
|
||||
.gpio27 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio0 = GPIO_INVERT,
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio8 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_NATIVE,
|
||||
.gpio37 = GPIO_MODE_NATIVE,
|
||||
.gpio38 = GPIO_MODE_NATIVE,
|
||||
.gpio39 = GPIO_MODE_NATIVE,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_GPIO,
|
||||
.gpio45 = GPIO_MODE_GPIO,
|
||||
.gpio46 = GPIO_MODE_GPIO,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_NATIVE,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_NATIVE,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_OUTPUT,
|
||||
.gpio44 = GPIO_DIR_OUTPUT,
|
||||
.gpio45 = GPIO_DIR_OUTPUT,
|
||||
.gpio46 = GPIO_DIR_OUTPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio35 = GPIO_LEVEL_HIGH,
|
||||
.gpio44 = GPIO_LEVEL_HIGH,
|
||||
.gpio45 = GPIO_LEVEL_HIGH,
|
||||
.gpio46 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0889, /* Codec Vendor / Device ID: Realtek */
|
||||
0x15d90644, /* Subsystem ID */
|
||||
15, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x15d90644),
|
||||
AZALIA_PIN_CFG(0, 0x11, 0x18561120),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x01011012),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x01016011),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19841),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181344f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4007e619),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x01c41150),
|
||||
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
AZALIA_PIN_CFG(3, 0x05, 0x58560010),
|
||||
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
/* FIXME: fix these values. */
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
Loading…
Reference in New Issue