From d025ab3bc2e2a9e116bfa43a3abf2f16ed4e7147 Mon Sep 17 00:00:00 2001 From: Varshit B Pandya Date: Tue, 29 Mar 2022 18:16:20 +0530 Subject: [PATCH] soc/intel/alderlake: Add HID for DPTF Power Participant BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device HID Signed-off-by: Varshit B Pandya Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/alderlake/dptf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c index 37754dbfae..59243baaeb 100644 --- a/src/soc/intel/alderlake/dptf.c +++ b/src/soc/intel/alderlake/dptf.c @@ -12,6 +12,8 @@ static const struct dptf_platform_info adl_dptf_platform_info = { .fan_hid = "INTC1048", /* _HID for the toplevel TPCH device, typically \_SB.TPCH */ .tpch_device_hid = "INTC1049", + /* _HID for the toplevel TPWR device, typically \_SB.DPTF.TPWR */ + .tpwr_device_hid = "INTC1060", .tpch_method_names = { .set_fivr_low_clock_method = "RFC0",